Method of fabrication of integrated circuit chip containing EEPROM and capacitor

Claim 1

A method of fabricating an IC device including an EEPROM cell, said method comprising performing the following steps in the order indicated: providing a semiconductor member having a flat surface; forming a first mask layer over said semiconductor member to define source/drain regions of a select transistor and a memory transistor within said EEPROM cell; implanting dopant into said semiconductor member using said first mask layer to form said source/drain regions; removing said first mask layer; growing a thick oxide on said surface of said semiconductor member; forming a second mask layer over said thick oxide layer to define a tunnel region of said memory transistor; etching said thick oxide layer using said second mask layer; removing said second mask layer; depositing a first conductive layer and depositing a dielectric layer over said first conductive layer; forming a third mask layer over said first conductive layer and said dielectric layer to define a floating gate of said memory transistor and a gate of said select transistor; etching said first conductive layer and said dielectric layer using said third mask layer to form the floating gate of said memory transistor and the gate of said select transistor; removing said third mask layer; growing a thin oxide layer on said surface of said semiconductor member in a region where a first low-voltage MOSFET is to be formed; depositing a second conductive layer over said dielectric layer and said thin oxide layer; forming a fourth mask layer to define a control gate of said memory transistor and a gate of said first low-voltage MOSFET; and etching said second conductive layer through said fourth mask layer to form the control gate of said memory transistor and the gate of said first low-voltage MOSFET.

Claim 2

A method of fabricating an IC device including an EEPROM cell, said method comprising performing the following steps in the order indicated: providing a semiconductor member having a flat surface; forming a first mask layer over said semiconductor member to define source/drain regions of a select transistor and a memory transistor within said EEPROM cell; implanting dopant into said semiconductor member using said first mask layer to form said source/drain regions; removing said first mask layer; growing a thick oxide on said surface of said semiconductor member; forming a second mask layer over said thick oxide layer to define a tunnel region of said memory transistor; etching said thick oxide layer using said second mask layer; removing said second mask layer; depositing a first conductive layer and depositing a dielectric layer over said first conductive layer; forming a third mask layer over said first conductive layer and said dielectric layer to define a floating gate of said memory transistor and a gate of said select transistor; etching said first conductive layer and said dielectric layer using said third mask layer to form the floating gate of said memory transistor and the gate of said select transistor; removing said third mask layer; growing a thin oxide layer on said surface of said semiconductor member in a region where a first low-voltage MOSFET is to be formed; depositing a second conductive layer over said dielectric layer and said thin oxide layer; forming a fourth mask layer to define a control gate of said memory transistor and a gate of said first low-voltage MOSFET; and etching said second conductive layer through said fourth mask layer to form the control gate of said memory transistor and the gate of said first low-voltage MOSFET.