EP0440265A2
Expired / Lapsed
EP
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Nonvolatile semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1988-01-29
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Granted: —
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Expires: 2008-01-29
Abstract
Abstract A nonvolatile semiconductor memory device comprises a cell transistor (32) formed of a floating gate type MOS transistor, for storing an electric charge, whose gate is connected to a control gate line layer (CG), a first selecting transistor (31) formed of an MOS transistor, whose gate is connected to a read gate line layer (RG), whose source-drain path is connected at one end to a read line layer (RL), and at the other end to one terminal of the source-drain path of the cell transistor, and a second selecting transistor (32) formed of an MOS transistor, whose gate is connected to a write gate line layer (WG), whose source-drain path is connected at one end to a write line layer (WL), and at the other end to the other terminal of the source-drain path of a cell transistor. A power source voltage (Vcc) of 5 V can be supplied to the read line layer (RL) in the read mode.
Inventors
- 👤 Tadashi C/O Patent Division Maruyama
- 👤 Yukio C/O Patent Division Wada
- 👤 Tomohisa C/O Patent Division Shigematsu
- 👤 Yasoji C/O Patent Division Suzuki
- 👤 Makoto Yoshizawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 17:50
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0433; G11C16/06; G11C16/10; G11C16/12; G11C16/14; G11C16/26; H; H10; H10B; H10B69/00; H10D; H10D30/00; H10D30/60; H10D30/68
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
175 words
A nonvolatile semiconductor memory device, characterized by comprising: a write line layer (WL); a read line layer (RL); a write gate line layer (WG, SG); a control gate line layer (CG); a read gate line layer (RG); a cell transistor (32) formed of a floating gate type MOS transistor, for storing an electric charge, whose control gate is connected to said control gate line layer; a first selecting transistor (31) formed of an MOS transistor, whose gate is connected to said read gate line layer, one terminal of whose source-drain path is connected to said read line layer, and the other terminal of the source-drain path is connected to one terminal of the source-drain path of said cell transistor; and a second selecting transistor (33) formed of an MOS transistor, whose gate is connected to said write gate line layer, one terminal of whose source-drain path is connected to said write line layer, and the other terminal of the source-drain path is connected to the other terminal of said source-drain path of said cell transistor.
Claim 2
Dependent Claim
28 words
The memory device according to claim 1, characterized in that said read gate line layer (RG) and said control gate line layer (CG) are interconnected with each other.
Claim 3
Dependent Claim
179 words
The memory device according to claim 2, characterized in that said write line layer (WL) applies to said one terminal of said source-drain path of said second selecting transistor a first voltage in the data write mode, and a second voltage lower than said first voltage in the data erase and read modes, said common gate line layer applies to said gates of said first selecting transistor (31) and said cell transistor (32) said first voltage in the data erase mode, said second voltage in the write mode, and a third voltage lower than said first voltage and higher than said second voltage in the read mode, said write gate line layer (SG) applies to said gate of said second selecting transistor (33) said first voltage in the data erase and write modes, and said third voltage in the data read mode, and said read line layer (RL) applies to said one terminal of said source-drain path of said first selecting transistor said second voltage in the data erase mode, and said third voltage in the data read mode.
Claim 4
Dependent Claim
43 words
The memory device according to claim 2, characterized in that said read line layer (RL) is connected to a power source (Vcc) via a load circuit (38), and a signal on the read line layer is supplied to a sense amplifier circuit (35).
Claim 5
Dependent Claim
23 words
The memory device according to claim 4, characterized in that said load circuit (38) comprises a MOS transistor (35) which normally turned on.
Claim 6
Dependent Claim
27 words
The memory device according to claim 4, characterized in that said load circuit (38) comprises a MOS transistor (36) which is turned on by a clock signal.
Claim 7
Dependent Claim
38 words
The memory device according to claim 6, characterized in that the voltage of said common gate line layer is supplied to said gates of said first and second selecting transistors (31, 33) in synchronism with said clock signal.
Claim 8
Dependent Claim
19 words
The memory device according to claim 4, characterized in that said sense amplifier circuit (35) is an inverter circuit.
Claim 9
Dependent Claim
28 words
The memory device according to claim 2, characterized in that said control gate line layer (CG) and said read gate line layer (RG) form a common gate line.
Claim 10
Dependent Claim
26 words
The memory device according to claim 2, characterized in that said first gate electrode (17) and said control gate electrode (23) are interconnected with each other.
References Cited (Backward Citations)
No citation records indexed.
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