Electrically alterable, nonvolatile, floating gate memory device

Claim 1

An electrically alterable, floating gate type, non­volatile, semiconductor memory device comprising a substrate of a semicondtuctor material having a channel region of a first type of conductivity contained between a first and a second region of a second type of conductivity, formed at the surface of said substrate of semiconductor material, said channel region providing a region in the semiconductor capable of passing an electric current between said first and said second region, a first level of conducting material forming a floating gate extending itself over said channel region between said first and said second region and over an injection area above one of said first or second region, and electrically insulated from the semiconductor material by a layer of gate oxide having an injection window within said injection area, the insulating layer within said window being represented by a layer of tunnel oxide, essentially thinner than the layer of gate oxide, and a second level of conducting material, insulated from said first level of conducting material and forming a control gate of the device, characterized in that in correspondence of said injection area, between said floating gate and the relevant one of said first or second region and with the exception of the area of said injection window, said insulating layer of gate oxide has a thickness greater than the thickness of said layer of gate oxide in correspondence of said channel region.

Claim 10

A method for fabricating a floating gate type, semiconductor memory device comprising a channel region between a drain region and a source region, and a floating gate of polycrystalline silicon, electrically insulated and overlying said channel region and said drain region over an injection area for the transfer of electrical charges by a tunnelling mechanism through an injection window of tunnel oxide located between said floating gate and said drain region, characterized by comprising: a) forming a first gate oxide layer over the area of a suitable substrate of semiconductor material where the device will be formed; b) masking the oxide layer formed during the preceding step a) in correspondence of said injection area between the drain region and the floating gate of the device and removing the layer of gate oxide already formed over an unmasked area in correspondence of said channel region; c) removing the masking material; d) forming a new layer of gate oxide over said channel region area and over the existing layer of gate oxide in correspondence of said injection area between the drain region and the floating gate of the device.

Claim 11

A method for fabricating a floating gate type, semiconductor memory device comprising a channel region between a drain region and a source region, and a floating gate of polycrystalline silicon, electrically insulated and overlying said channel region and said drain region over an injection area for the transfer of electrical charges by a tunnelling mechanism through an injection window of tunnel oxide located between said floating gate and said drain region, characterized by comprising: a) forming a first gate oxide layer over the area of a suitable substrate of semiconductor material where the device will be formed; b) masking the oxide layer formed during the preceding step a) in correspondence of said injection area between the drain region and the floating gate of the device and removing the layer of gate oxide already formed over an unmasked area in correspondence of said channel region; c) removing the masking material; d) forming a new layer of gate oxide over said channel region area and over the existing layer of gate oxide in correspondence of said injection area between the drain region and the floating gate of the device.