EP0146356A2
Expired / Lapsed
EP
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Static memory cell having electrical elements on two levels
Assignee: Fujitsu Ltd
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Filing: 1984-12-14
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Granted: —
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Expires: 2004-12-14
Abstract
Abstract A static MOS memory device having a double polysilicon structure has parasitic transistors (Q 5 , Q 6 ). The arrangement of electrical elements, transistors (Q 1 , Q 2 ) and resistors (R 1 , R 2 ), making up a memory cell, which are arranged in two overlapping layers, is such that the associated parasitic transistors (Q 5 , Q 6 ) are maintained non-conductive regardless of the state of the memory cell, that is the state «1» or «0» of the cell, thereby avoiding an enhancement of memory cell current due to the presence of the parasitic transistors (Q 5 , Q 6 ). Each parasitic transistor (Q 5 , Q 6 ) has its gate electrode and source commonly connected.
Inventors
- 👤 Takahiko C/O Fujitsu Limited Yamauchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 08:16
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; H; H10; H10B; H10B10/00; H10B10/15; H10D; H10D84/00
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
174 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first field effect transistor being connected in series with one another, connected to one another at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series with one another, connected to one another at a second node; and said first gate electrode being connected to said second node, and said second gate electrode being connected to said first node, and said first and second resistors being formed at a level above the first and second transistors, separated from the first and second transistors by an insulator layer, wherein the first and second resistors are positioned to overlie respective elements forming the transistors, such an element being a gate electrode or a source-drain region, which elements are connected to the first and second nodes respectively.
Claim 2
Dependent Claim
174 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first field effect transistor being connected in series with one another, connected to one another at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series with one another, connected to one another at a second node; and said first gate electrode being connected to said second node, and said second gate electrode being connected to said first node, and said first and second resistors being formed at a level above the first and second transistors, separated from the first and second transistors by an insulator layer, wherein the first and second resistors are positioned to overlie respective elements forming the transistors, such an element being a gate electrode or a source-drain region, which elements are connected to the first and second nodes respectively.
Claim 3
Dependent Claim
143 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first field effect transistor being connected in series at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series at a second node; and a power supply line to which said first and second resistors are connected, said first gate electrode being connected to said second node, said second gate electrode being connected to said first node, said first resistor being positioned over said second gate electrode and said second resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said second node.
Claim 4
Dependent Claim
143 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first field effect transistor being connected in series at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series at a second node; and a power supply line to which said first and second resistors are connected, said first gate electrode being connected to said second node, said second gate electrode being connected to said first node, said first resistor being positioned over said second gate electrode and said second resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said second node.
Claim 5
Dependent Claim
170 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first transistor being connected in series at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series at a second node; and a power supply line to which said first and second resistors are connected, said first gate electrode being connected to said second node, said second gate electrode being connected to said first node, said first resistor and said second resistor are connected to said power supply line, said first resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said first node, and said second resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said second node.
Claim 6
Dependent Claim
170 words
A static memory cell comprising: a first resistor and a first field effect transistor having a first gate electrode and source-drain regions, said first resistor and said first transistor being connected in series at a first node; a second resistor and a second field effect transistor having a second gate electrode and source-drain regions, said second resistor and said second field effect transistor being connected in series at a second node; and a power supply line to which said first and second resistors are connected, said first gate electrode being connected to said second node, said second gate electrode being connected to said first node, said first resistor and said second resistor are connected to said power supply line, said first resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said first node, and said second resistor being positioned over the one of said source-drain regions of said second field effect transistor which is connected to said second node.
References Cited (Backward Citations)
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