US5305263A
Expired / Lapsed
US
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Simplified low power flash write operation
Assignee: Micron Technology Inc
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Filing: 1991-06-12
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Granted: 1994-04-19
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Expires: 2011-06-12
Abstract
Abstract In the preferred embodiment of the present invention flash write, a simultaneous and substantially identical write operation to a selected plurality of memory cells, is performed by splitting the pull up of the p sense amplifier transistors. The p sense amplifier transistor on digit is connected to V cc at its drain through a first pull up transistor and the p sense amplifier transistor on digit bar is connected to V cc at its drain through a second pull up transistor. A logic circuit generates control logic that actuates either both pull up transistors to initiate a typical read/write operation of a single memory cell or actuates one of the two pull up transistors to initiate a flash write to all of the memory cells on the selected wordline.
Inventors
- 👤 Donald M. Morgan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:59
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4096; G11C7/00; G11C7/12; G11C7/20
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
444 words
A memory circuit comprising: a) a first node connectable to a first potential corresponding to a first logic state; b) a second node connectable to a second potential corresponding to said first logic state; c) a third node connectable to a third potential corresponding to a second logic state; d) a first input/output line (186A) for accepting electrical input data and for providing electrical output data; e) a first memory storage cell (171) for storing said electrical input data and said electrical output data; f) a first digit (165) line for transferring said electrical input data and said electrical output data between said first input/output line (186A) and said first memory storage cell (171), said first input/output line (186A) electrically coupled to said first digit line (165); g) a second input/output line (186B) for accepting a complement of said electrical input data and for providing a complement of said electrical output data; h) a second memory storage cell (181) for storing said complement of said electrical input data and said complement of said electrical output data; i) a second digit line (160) for transferring said electrical input data and said electrical output data between said second input/output line (186B) and said second memory storage cell (181), said second input/output line (186B) electrically coupled to said second digit line (160); j) a first switching device (82, 301) electrically interposed between said first node and said first digit line (165); k) a first switching device (82, 301) electrically interposed between said second node and said second digit line (160); l) a third switching device (145, 303) electrically interposed between said third node and said first digit line (165) and electrically interposed between said third node and said second digit line (160); m) a first sense circuit (85) electrically coupled between both said first (165) and said second (160) digit lines, said first sense circuit (85) capable of electrically isolating said first digit line (165) from said first switching device (82, 301) and capable of electrically isolating said second digit line (160) from said second switching device (83, 302), said first sense circuit capable of sensing and latching said first and second digit lines to potentials having said first and second logic states; and n) a second sense circuit (95) electrically coupled between both said first (165) and said second (160) digit lines, said second (95) sense circuit capable of electrically isolating said first digit line (165) and said second (160) digit line from said third switching device (145, 303), said second sense circuit (95) capable of sensing and latching said first (165) and second (160) digit lines to potentials having said first and second logic states.
Claim 2
Dependent Claim
444 words
A memory circuit comprising: a) a first node connectable to a first potential corresponding to a first logic state; b) a second node connectable to a second potential corresponding to said first logic state; c) a third node connectable to a third potential corresponding to a second logic state; d) a first input/output line (186A) for accepting electrical input data and for providing electrical output data; e) a first memory storage cell (171) for storing said electrical input data and said electrical output data; f) a first digit (165) line for transferring said electrical input data and said electrical output data between said first input/output line (186A) and said first memory storage cell (171), said first input/output line (186A) electrically coupled to said first digit line (165); g) a second input/output line (186B) for accepting a complement of said electrical input data and for providing a complement of said electrical output data; h) a second memory storage cell (181) for storing said complement of said electrical input data and said complement of said electrical output data; i) a second digit line (160) for transferring said electrical input data and said electrical output data between said second input/output line (186B) and said second memory storage cell (181), said second input/output line (186B) electrically coupled to said second digit line (160); j) a first switching device (82, 301) electrically interposed between said first node and said first digit line (165); k) a first switching device (82, 301) electrically interposed between said second node and said second digit line (160); l) a third switching device (145, 303) electrically interposed between said third node and said first digit line (165) and electrically interposed between said third node and said second digit line (160); m) a first sense circuit (85) electrically coupled between both said first (165) and said second (160) digit lines, said first sense circuit (85) capable of electrically isolating said first digit line (165) from said first switching device (82, 301) and capable of electrically isolating said second digit line (160) from said second switching device (83, 302), said first sense circuit capable of sensing and latching said first and second digit lines to potentials having said first and second logic states; and n) a second sense circuit (95) electrically coupled between both said first (165) and said second (160) digit lines, said second (95) sense circuit capable of electrically isolating said first digit line (165) and said second (160) digit line from said third switching device (145, 303), said second sense circuit (95) capable of sensing and latching said first (165) and second (160) digit lines to potentials having said first and second logic states.
Claim 3
Dependent Claim
63 words
The memory circuit as specified in claim 1, wherein a first signal actuates both said first (82, 301) and said second (83, 302) switching devices during a normal read/write operation of the memory circuit, and wherein a second signal actuates only one of said first (82, 301) and said second (83, 302) switching devices during a flash write operation of the memory circuit.
Claim 4
Dependent Claim
82 words
The memory circuit as specified in claim 2, further comprising a first decode transistor for isolating said first input/output line (186A) from said first digit line (165) and a second decode transistor for isolating said second input/output line (186B) from said second digit line (160) during said flash write operation and for coupling said first input/output line (186A) to said first digit line (165) and for coupling said second input/output line (186B) to said second digit line (160) during said read/write operation.
Claim 5
Dependent Claim
91 words
The memory circuit as specified in claim 2, further comprising a first access transistor (173) electrically interposed between said first memory storage cell (171) and said first digit line (165) and a second access transistor (183) electrically interposed between said second memory storage cell (181) and said second digit line (160), said first (173) and said second (183) access transistors actuated when said electrical input data is written to said first (171) and said second (181) memory storage cells during said flash write operation and during said normal read write operation.
Claim 6
Dependent Claim
22 words
The memory circuit as specified in claim 2, further comprising a control circuit (140) for generating said first and said second signals.
Claim 7
Dependent Claim
35 words
The memory circuit as specified in claim 5, wherein said control circuit (140) responds to a read/write firing signal having an inactive state for allowing said first (165) and second (160) digit lines to equilibrate.
Claim 8
Dependent Claim
42 words
The memory circuit as specified in claim 5, wherein said control circuit (140) responds to a data bit having a logic state to be written to said first digit line (165) or said second digit line (160) during said flash write operation.
Claim 9
Dependent Claim
57 words
The memory circuit as specified in claim 5, wherein said control circuit (140) responds to a flash/write enable signal, an active state of said flash write enable signal enables said control circuit (140) to generate said second signal, and an inactive state of said flash write enable signal enables said control circuit to generate said first signal.
Claim 10
Dependent Claim
24 words
The memory circuit as specified in claim 5, wherein said control circuit (140) responds to a masking signal to inhibit said flash write operation.
Claim 11
Dependent Claim
88 words
The memory circuit as specified in claim 2, further comprising: a) a first plurality of said first digit lines (165); and b) a second plurality of said second digit lines (160) such that during said flash write operation said electrical input data is substantially simultaneously written to said memory storage cell electrically coupled to each of said first digit lines (165) of said first plurality or substantially simultaneously written to said memory storage cell electrically coupled to each of said second digit lines (160) of said second plurality.
Claim 12
Dependent Claim
103 words
The memory circuit as specified in claim 10, further comprising: a) a first switch plurality of said first switching devices (82, 301), wherein each said first digit line (165) of said first plurality of said first digit lines (165) is electrically coupled to one of said first switching devices (82, 301) of said first switch plurality; and b) a second switch plurality of said second switching devices (83, 302), wherein each said second digit line (160) of said second plurality of said second digit lines (160) is electrically coupled to one of said second switching devices (83, 302) of said second switch plurality.
Claim 13
Dependent Claim
77 words
The memory circuit as specified in claim 1, further comprising a fourth switching device (310) electrically interposed between an output of said first switching device (301) and an output of said second switching device (302), said fourth switching device (310) coupling an output of said first (301) and an output of said second (302) switching device to a common node in order to reduce voltage sensitivity affects of said first (302) and said second (302) switching devices.
Claim 14
Dependent Claim
18 words
The memory circuit as specified in claim 1, wherein said first and said second potentials are the same.
Claim 15
Independent Claim
160 words
A method for writing to a memory cell, comprising the following steps: a) actuating a first switching device (82, 301) electrically coupled to a first plurality of digit lines (165) and electrically coupled to a first potential corresponding to a first logic state; b) deactuating a second switching device (83, 302) electrically coupled to a second plurality of digit lines (160) and electrically coupled to said first potential; c) actuating a third switching device (145, 303) electrically coupled to said first and said second pluralities and electrically coupled to a second potential corresponding to a second logic state; d) latching a potential having said first logic state to said first plurality; e) latching a potential having said second logic state to said second plurality; f) isolating said second plurality from said first potential; and g) writing electrical input data substantially simultaneously to at least one memory cell (171) electrically coupled to each said digit line (165) of said first plurality.
Claim 16
Independent Claim
160 words
A method for writing to a memory cell, comprising the following steps: a) actuating a first switching device (82, 301) electrically coupled to a first plurality of digit lines (165) and electrically coupled to a first potential corresponding to a first logic state; b) deactuating a second switching device (83, 302) electrically coupled to a second plurality of digit lines (160) and electrically coupled to said first potential; c) actuating a third switching device (145, 303) electrically coupled to said first and said second pluralities and electrically coupled to a second potential corresponding to a second logic state; d) latching a potential having said first logic state to said first plurality; e) latching a potential having said second logic state to said second plurality; f) isolating said second plurality from said first potential; and g) writing electrical input data substantially simultaneously to at least one memory cell (171) electrically coupled to each said digit line (165) of said first plurality.
Claim 17
Dependent Claim
35 words
The method as specified in claim 14, further comprising writing complementary electrical input data substantially simultaneously to at least one memory cell (181) electrically coupled to each said digit line (160) of said second plurality.
Claim 18
Independent Claim
275 words
A method for driving electrical data to a digit line, comprising the following steps: a) actuating a first transistor (145, 303) electrically coupled to a first potential and electrically coupled to a first (165) and a second (160) digit line, said first potential corresponding to a first logic state; b) in a flash write operation, deactuating a decode device in order to isolate a first (186A) and a second (186B) input/output line from said first (165) and said second (160) digit lines, respectively; and generating first control signals to actuate a second transistor (82, 301) electrically coupled to said first digit line (165) and deactuate a third transistor (83, 302) electrically coupled to a second digit line (160), said second (82, 301) and said third (83, 302) transistors electrically coupled to a second potential corresponding to a second logic state, said deactuated third transistor (83, 302) isolating said second digit line (160) from said second potential, and said actuated second transistor (82, 301) driving said first digit line (165) to potential having said first logic state; and c) in a read/write operation, actuating said decode device to provide electrical continuity between said first input/output line (186A) and said first digit line (165) and to provide electrical continuity between said second input/output line (186B) and said second digit line (160); and generating second control signals to actuate both said second (82, 301) and said third (83, 302) transistors, thereby driving a potential having one of said first and second logic states from said first input/output line (186A) to said first digit line (165) and from said second input/output line (186B) to said second digit line (160).
Claim 19
Independent Claim
275 words
A method for driving electrical data to a digit line, comprising the following steps: a) actuating a first transistor (145, 303) electrically coupled to a first potential and electrically coupled to a first (165) and a second (160) digit line, said first potential corresponding to a first logic state; b) in a flash write operation, deactuating a decode device in order to isolate a first (186A) and a second (186B) input/output line from said first (165) and said second (160) digit lines, respectively; and generating first control signals to actuate a second transistor (82, 301) electrically coupled to said first digit line (165) and deactuate a third transistor (83, 302) electrically coupled to a second digit line (160), said second (82, 301) and said third (83, 302) transistors electrically coupled to a second potential corresponding to a second logic state, said deactuated third transistor (83, 302) isolating said second digit line (160) from said second potential, and said actuated second transistor (82, 301) driving said first digit line (165) to potential having said first logic state; and c) in a read/write operation, actuating said decode device to provide electrical continuity between said first input/output line (186A) and said first digit line (165) and to provide electrical continuity between said second input/output line (186B) and said second digit line (160); and generating second control signals to actuate both said second (82, 301) and said third (83, 302) transistors, thereby driving a potential having one of said first and second logic states from said first input/output line (186A) to said first digit line (165) and from said second input/output line (186B) to said second digit line (160).
Claim 20
Dependent Claim
39 words
The method as specified in claim 16, further comprising substantially simultaneously driving a plurality of said first digit lines (165) to a potential of said first logic state in response to said step of generating said first control signals.
Claim 21
Dependent Claim
47 words
The method as specified in claim 17, further comprising actuating an access transistor (173) interposed between each of said first digit lines (165) and a memory storage cell (171) in order to write the electrical data having said first logic state to said memory storage cell (171).
Claim 22
Dependent Claim
39 words
The method as specified in claim 16, further comprising substantially simultaneously driving a plurality of said second digit lines (160) to a potential having said second logic state in response to said step of generating said first control signals.
Claim 23
Dependent Claim
48 words
The method as specified in claim 19, further comprising actuating an access transistor (183) electrically interposed between each of said second digit lines (160) and a memory storage cell (181) in order to write the electrical data having said second logic state to said memory storage cell (181).
Claim 24
Dependent Claim
32 words
The method as specified in claim 16, further comprising driving only one first digit line (165) of said plurality of first digit lines to one of said first or second logic states.
Claim 25
Dependent Claim
51 words
The method as specified in claim 21, further comprising actuating an access transistor (173) electrically interposed between each of said first digit lines (165) and a memory storage cell (171) in order to write the electrical data having said first or said second logic state to said memory storage cell (171).
Claim 26
Dependent Claim
82 words
The method as specified in claim 16, further comprising: a) actuating a fourth transistor (310) during said step of generating said second control signal in order to couple an output of said second transistor (301) and an output of said third transistor (302) to a common node; and b) deactuating said fourth transistor (310) during said step of generating said first control signals in order to isolate said outputs of said second (301) and said third transistors (302) one from the other.
Claim 27
Dependent Claim
18 words
The method as specified in claim 16, further comprising inhibiting said step of generating said first control signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-04-18 | 1997-10-18 | 1998-04-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-04-18 | 2001-10-18 | 2002-04-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-04-18 | 2005-10-18 | 2006-04-19 | $7700.00 | Window Closed / Lapsed |