Flash writing circuit for writing test data in dynamic random access memory (dram) devices

Claim 1

A flash writing circuit for writing test data into a dynamic random access memory device, said device comprising a plurality of memory cells arrayed in rows and columns of memory cells, a plurality of word lines, each accessing a respective row of cells, a plurality of pairs of bit lines, each pair accessing a respective column of cells, a plurality of pairs of input/output lines, each pair of bit lines being connected to one of said pairs of input/output lines, a plurality of sense amplifiers each connected between a corresponding pair of bit lines and one of said pairs of input/output lines, with flash writing circuit comprising: equalizing and connecting means for equalizing a potential level on all of said bit lines, said equalizing and connecting means comprising a plurality of first metal oxide semiconductor (MOS) transistors, each first MOS transistor respectively connected between the bit lines of a corresponding bit line pair, and a plurality of pairs of second MOS transistors, each second MOS transistor having a first source/drain electrode connected to a respective one of the bit lines, a node connecting means connecting to said equalizing and connecting means for providing a signal path from a flash write signal generating means to each of the bit lines, said flash write signal generating means being connected to said node connecting means for providing a difference voltage across the bit lines of each bit line pair, whereby the same data is written to all the memory cells accessed by a selected word line without the use of said input/output lines, said node connecting means comprising a pair of conductive paths extending between said flash write signal generating means and each bit line pair, each of said conductive paths connected to a second source/drain electrode of a plurality of said second MOS transistors, said flash write signal generating means comprising a third MOS transistor for equalizing voltage levels on said conductive paths, a plurality of fourth MOS transistors for supplying said test data by providing predetermined voltage levels to each of said conductive paths in response to control logic signals, and fifth and sixth MOS transistors each having a source/drain path connected between a respective one of said conductive paths and a precharge potential source for applying a precharge potential level to said conductive paths.