US4587629A
Expired / Lapsed
US
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Random address memory with fast clear
Assignee: International Business Machines Corp
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Filing: 1983-12-30
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Granted: 1986-05-06
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Expires: 2003-12-30
Abstract
Abstract A technique and apparatus for augmenting a random access memory with a fast clear or reset mechanism are described. A dynamic RAM having a fast clear mechanism in accordance with the present invention includes means for coupling a digital signal onto all bit lines; and fast reset control means operative for energizing the coupling means for connecting the digital signal to all of the bit lines such that upon energizing of a selected word line, all the bits connected to the selected word line are reset to the state of the digital signal, whereby reset time of the random access memory is reduced. The present invention is especially beneficial for incorporation in a frame buffer of an all points addressable raster scan display, and in a page buffer of an all points addressable printer wherein there is a requirement for high update performance.
Inventors
- 👤 Frederick H. Dill
- 👤 Satish Gupta
- 👤 Peter J. Warter
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 04:46
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
155 words
In an integrated circuit random access memory array having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 2
Dependent Claim
155 words
In an integrated circuit random access memory array having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 3
Dependent Claim
27 words
In an integrated circuit random address memory array as set forth in claim 1, wherein said signal is digital having either a logical 1 or 0 state.
Claim 4
Dependent Claim
24 words
In an integrated circuit random address memory array as set forth in claim 2, wherein said random address memory array is a dynamic RAM.
Claim 5
Dependent Claim
167 words
A display having a memory subsystem comprising a plurality of improved integrated circuit random access memory arrays, each characterized by having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 6
Dependent Claim
167 words
A display having a memory subsystem comprising a plurality of improved integrated circuit random access memory arrays, each characterized by having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 7
Dependent Claim
28 words
A display as set forth in claim 4, wherein said memory subsystem is a frame buffer, and wherein said display is an all points addressable raster scan display.
Claim 8
Dependent Claim
18 words
A display as set forth in claim 5, wherein said random address memory array is a dynamic RAM.
Claim 9
Dependent Claim
167 words
A printer having a memory subsystem comprising a plurality of improved integrated circuit random access memory arrays, each characterized by having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 10
Dependent Claim
167 words
A printer having a memory subsystem comprising a plurality of improved integrated circuit random access memory arrays, each characterized by having a plurality of words of storage capacity, each of said words being arranged in a column of bits connected to a word line, the bits of said words forming rows and having all the bits in each row connected to a bit line, means for addressing each word line and each bit line for writing in a selected bit to establish the state of the selected bit line, and a sense amplifier for each bit line for sensing the selected bit, the improvement comprising: means for coupling a signal onto said bit lines; and fast reset control means connected to said coupling means for connecting said signal to said bit lines, and upon energizing of a selected word line, all the bits connected to said selected word line are reset to the state of said signal, whereby reset time of said random access memory is reduced.
Claim 11
Dependent Claim
26 words
A printer as set forth in claim 7, wherein said memory subsystem is a page buffer, and wherein said printer is an all points addressable printer.
Claim 12
Dependent Claim
18 words
A printer as set forth in claim 8, wherein said random address memory array is a dynamic RAM.
References Cited (Backward Citations)
US4314353A
Cited
US4513374A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-05 | 1989-11-04 | 1990-05-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-05 | 1993-11-04 | 1994-05-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-05 | 1997-11-04 | 1998-05-06 | $7700.00 | Window Closed / Lapsed |