Electrically alterable non-volatile memory with n-bits per cell

Claim 2

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of said first to third states is selected, verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 3

The method of operating the electrically alterable non-volatile multi-level memory according to claim 1 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 4

The method of operating the electrically alterable non-volatile multi-level memory according to claim 2 , wherein the operation of setting the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 5

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of said first to third states is selected, verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, including comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 6

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of said first to third states is selected, verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, including comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 7

The method of operating the electrically alterable non-volatile multi-level memory according to claim 4 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 8

The method of operating the electrically alterable non-volatile multi-level memory according to claim 5 , wherein the operation of controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 9

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of the first to third states is selected, verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 10

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of the first to third states is selected, verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state, including comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 11

The method of operating the electrically alterable non-volatile multi-level memory according to claim 7 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 12

The method of operating the electrically alterable non-volatile multi-level memory according to claim 8 , wherein the operation of setting the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 13

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of said first to third states is selected, verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, including comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 14

For an electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, a method of operating the electrically alterable non-volatile multi-level memory device, comprising: controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, when one of said first to third states is selected, verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, including comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, reading status of the one non-volatile multi-level memory cell, including comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 15

The method of operating the electrically alterable non-volatile multi-level memory according to claim 10 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 16

The method of operating the electrically alterable non-volatile multi-level memory according to claim 11 , wherein the operation of controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 17

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing substantially in a same direction, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of the first to third states is selected, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 18

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing substantially in a same direction, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and the third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of the first to third states is selected, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 19

The electrically alterable non-volatile multi-level memory according to claim 13 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 20

The electrically alterable non-volatile multi-level memory according to claim 14 , wherein the operation of setting the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 21

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 22

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by hot electron injection from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 23

The electrically alterable non-volatile multi-level memory according to claim 16 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 24

The electrically alterable non-volatile multi-level memory according to claim 17 , wherein the operation of controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 25

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 26

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of setting a parameter of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the parameter of the one non-volatile multi-level memory cell has been set to the one state is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with one of a plurality of verifying reference parameters including at least a first verifying reference parameter, a second verifying reference parameter and a third verifying reference parameter, and the operation of setting the parameter is conducted until it is verified by the operation of verifying that the parameter of the one non-volatile multi-level memory cell has been set to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the parameter of the one non-volatile multi-level memory cell with a plurality of reading reference parameters including at least a first reading reference parameter, a second reading reference parameter and a third reading reference parameter, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference parameter is allocated between the first state and the second state, the second reading reference parameter is allocated between the second state and the third state, and the third reading reference parameter is allocated between the third state and the fourth state, wherein the first reading reference parameter, the second reading reference parameter and the third reading reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter of the one non-volatile multi-level memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference parameter, a second input terminal of the second sense circuit is supplied with the second reading reference parameter and a second input terminal of the third sense circuit is supplied with the third reading reference parameter, and wherein the first verifying reference parameter is allocated above the first reading reference parameter, the second verifying reference parameter is allocated between the first reading reference parameter and the second reading reference parameter and the third verifying reference parameter is allocated between the second reading reference parameter and the third reading reference parameter.

Claim 27

The electrically alterable non-volatile multi-level memory according to claim 19 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of setting the parameter includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 28

The electrically alterable non-volatile multi-level memory according to claim 20 , wherein the operation of setting the parameter includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi-level memory cell.

Claim 29

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 30

An electrically alterable non-volatile multi-level memory device including a plurality of non-volatile multi-level memory cells, each of the multi-level memory cells including a floating gate FET having a channel with electrically alterable voltage threshold value, the plurality of non-volatile multi-level memory cells being disposed in a matrix of rows and columns, channels of multi-level memory cells of a first group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a first bit line and a reference potential, channels of multi-level memory cells of a second group of the plurality of non-volatile multi-level memory cells being coupled in parallel between a second bit line and the reference potential, electrons being capable of being injected into the floating gate by Fowler-Nordheim tunneling from the channel in each of the plurality of non-volatile multi-level memory cells, electric currents flowing through the channels of the multi-level memory cells of the first group and electric currents flowing through the channels of the multi-level memory cells of the second group flowing in substantially a same direction, wherein an operation of controlling an electrical value of at least one non-volatile multi-level memory cell of the plurality of non-volatile multi-level memory cells to a state selected from a plurality of states including at least a first state, a second state, a third state and a fourth state is carried out in response to information to be stored in the one non-volatile multi-level memory cell, wherein the first, the second and third state indicate mutually different programming states and the fourth state indicates an erase state, wherein, when one of said first to third states is selected, an operation of verifying whether the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with one of a plurality of verifying reference electrical values including at least a first verifying reference electrical value, a second verifying reference electrical value and a third verifying reference electrical value, and the operation of controlling the electrical value is conducted until it is verified by the operation of verifying that the electrical value of the one non-volatile multi-level memory cell has been controlled to the one state, wherein an operation of reading status of the one non-volatile multi-level memory cell is carried out and includes comparing the electrical value of the one non-volatile multi-level memory cell with a plurality of reading reference electrical values including at least a first reading reference electrical value, a second reading reference electrical value and a third reading reference electrical value, wherein a conductivity value of the one non-volatile multi-level memory cell is changed in order of the first state, the second state, the third state and the fourth state, wherein the first reading reference electrical value is allocated between the first state and the second state, the second reading reference electrical value is allocated between the second state and the third state, and the third reading reference electrical value is allocated between the third state and the fourth state, wherein the first reading reference electrical value, the second reading reference electrical value and the third reading reference electrical value are electrical values for a normal read operation in which the information stored in the one non-volatile multi-level memory cell can be read out by output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the electrical value of the one non-volatile multi-level memory cell with the plurality of reading reference electrical values using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the electrical value from the one non-volatile multi-level memory cell, a second input terminal of the first sense circuit is supplied with the first reading reference electrical value, a second input terminal of the second sense circuit is supplied with the second reading reference electrical value and a second input terminal of the third sense circuit is supplied with the third reading reference electrical value, and wherein the first verifying reference electrical value is allocated above the first reading reference electrical value, the second verifying reference electrical value is allocated between the first reading reference electrical value and the second reading reference electrical value and the third verifying reference electrical value is allocated between the second reading reference electrical value and the third reading reference electrical value.

Claim 31

The electrically alterable non-volatile multi-level memory according to claim 22 , wherein a conductivity value of the one non-volatile multi-level memory cell is increased in order of the first state, the second state, the third state and the fourth state, and wherein the operation of controlling the electrical value includes an erasure operation in which non-volatile multi-level memory cells of one of a byte, a block and a chip level can be erased.

Claim 32

The electrically alterable non-volatile multi-level memory according to claim 23 , wherein the operation of controlling the electrical value includes a program operation in which electrons are injected into a floating gate of the one non-volatile multi- level memory cell.