Electrically alterable non-volatile memory with n-bits per cell

Claim 1

A non-volatile semiconductor memory device comprising: a plurality of non-volatile memory cells each of which has a floating gate, a drain coupled to a bit line and a threshold voltage representing data of a least two bits, wherein electrons are capable of being injected into the floating gate, and wherein threshold voltages of the plurality of non-volatile memory cells are shiftable among at least three threshold levels which indicate mutually different programming states and which also differ from a threshold level indicating an erase state; and sensing/program-verifying circuitry receiving a parameter which represents the threshold voltage of one non-volatile memory cell, a first programming reference parameter, a first read reference parameter, a second programming reference parameter, a second read reference parameter, a third programming reference parameter and a third read reference parameter; wherein the first read reference parameter is allocated between the threshold level indicating the erase state and the first programming reference parameter, the second read reference parameter is allocated between the first programming reference parameter and the second programming reference parameter, and the third read reference parameter is allocated between the second programming reference parameter and the third programming reference parameter, wherein the sensing/program-verifying circuitry generates data of at least two bits represented by the one non-volatile memory cell threshold voltage, verifies whether the one non-volatile memory cell threshold voltage is shifted to the threshold level indicating a selected one of the programming states, and programs the one non-volatile memory cell until it is verified that the one non-volatile memory cell threshold voltage has been shifted to that threshold level, wherein the first programming reference parameter is used for verifying whether non-volatile memory cell threshold voltages are shifted to a first threshold level of the three threshold levels, the first read reference parameter is used for detecting whether non-volatile memory cell threshold voltages are near to the first threshold level or to the threshold level indicating the erase state, wherein the second programming reference parameter is used for verifying whether non-volatile memory cell threshold voltages are shifted to a second threshold level of the three threshold levels, the second read reference parameter is used for detecting whether non-volatile memory cell threshold voltages are near to the second threshold level or to the first threshold level, wherein the third programming reference parameter is used for verifying whether non-volatile memory cell threshold voltages are shifted to a third threshold level of the three threshold levels, the third read reference parameter is used for detecting whether non-volatile memory cell threshold voltages are near to the third threshold level or to the second threshold level, wherein the first read reference parameter, the second read reference parameter and the third read reference parameter are parameters for a normal read operation in which the information stored in the one non-volatile memory cell can be read out as output data of a plurality of bits, wherein the normal read operation includes parallel-comparing the parameter re presenting the threshold voltage of the one non-volatile memory cell with the plurality of reading reference parameters using a plurality of sense circuits including at least a first sense circuit, a second sense circuit and a third sense circuit, first input terminals of the first sense circuit, the second sense circuit and the third sense circuit are commonly supplied with the parameter representing the threshold voltage of the one non-volatile memory cell, a second input terminal of the first sense circuit is supplied with the first read reference parameter, a second input terminal of the second sense circuit is supplied with the second read reference parameter and a second input terminal of the third sense circuit is supplied with the third read reference parameter, wherein the plurality of non-volatile memory cells are arranged in a matrix of rows and columns and disposed in substantially a rectangle that has a first side, a second side, a third side and a fourth side, the first side and the second side intersect with each other substantially perpendicularly, a plurality of word lines coupled with gate electrodes of the floating gates of the non-volatile memory cells and the first side of the rectangle intersect with each other substantially perpendicularly, a plurality of bit lines coupled with drains of the non-volatile memory cells and the second side of the rectangle intersect with each other substantially perpendicularly, a row select circuit is disposed at the first side of the rectangle for coupling with the plurality of word lines, and peripheral circuitry, which includes a column select circuit, sense circuits, a data conversion circuit and latches, is disposed at the second side of the rectangle, wherein an operation of shifting the threshold voltage of the one non-volatile memory cell to the threshold level indicating the selected programming state includes a program operation, in which electrons are injected into the floating gate of the one non-volatile memory cell by applying a plurality of programming pulses to the bit line coupled with the drain of the one non-volatile memory cell, and wherein the plurality of programming pulses includes at least a first programming pulse and a second programming pulse after the first programming pulse, a parameter of the first programming pulse has a first predetermined value and a same parameter of the second programming pulse has a second predetermined value that is substantially different from the first predetermined value.