Patent US6314530B1 successfully refreshed from Google Patents.
US6314530B1
Expired / Lapsed
US
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Processor having a trace access instruction to access on-chip trace memory
Assignee: GlobalFoundries Inc
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Filing: 1997-12-17
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Granted: 2001-11-06
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Expires: 2017-12-17
Abstract
Abstract A computer system includes a memory for storing instructions executable by a processor and an on-chip trace memory having a plurality of locations for storing trace information that indicates execution flow in the processor. A trace access instruction provides for access to the on-chip trace memory on the processor. The trace access instruction can be a write instruction or a read instruction. Typically, both read and write to the trace memory is provided. The system also has the capability to trace on start or restart of an executable thread by providing to the processor an indication of which executable thread to trace via a debug port. That indicates to the processor to provide trace information when the executable thread starts. When execution of the executable thread starts, the processor places an identifier corresponding to the executable thread into the trace memory to indicate that subsequent entries placed into the trace memory are part of said executable thread. The processor may also provide an entry indicating when the thread stops executing.
Inventors
- 👤 Daniel Mann
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 08:19
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/36; G06F11/362; G06F11/3636; G06F11/30; G06F11/34; G06F11/3466; G06F11/348; G06F11/3648; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1036
Claims Analysis
Total Claims: 40
Claim 1
Independent Claim
63 words
A method of operating a computer system including a processor, comprising: said processor executing a trace access instruction stored in a memory for storing instructions executable by said processor, to access an on-chip trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of execution flow of a plurality of said instructions in said processor.
Claim 2
Independent Claim
63 words
A method of operating a computer system including a processor, comprising: said processor executing a trace access instruction stored in a memory for storing instructions executable by said processor, to access an on-chip trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of execution flow of a plurality of said instructions in said processor.
Claim 3
Dependent Claim
36 words
The method as recited in claim 1 wherein said trace access instruction is a write instruction, said write instruction writing data identified by said trace access instruction to one of said locations in said trace memory.
Claim 4
Dependent Claim
60 words
The method as recited in claim 2 further comprising executing a second trace access instruction stored in said memory, and wherein said second trace access instruction is a read instruction, said read instruction reading data from one of said locations in said trace memory, said one location containing data indicative of execution flow of previously executed instructions of said processor.
Claim 5
Dependent Claim
46 words
The method as recited in claim 1 wherein said trace access instruction is a read instruction, said read instruction reading data from one of said locations in said trace memory, said one location containing data indicative of execution flow of previously executed instructions of said processor.
Claim 6
Dependent Claim
48 words
The method as recited in claim 4 further comprising executing a second trace access instruction stored in said memory, and wherein said second trace access instruction is a write instruction writing data identified by said second trace access instruction to one of said locations in said trace memory.
Claim 7
Dependent Claim
72 words
The method as recited in claim 1 further comprising: providing to said processor an indication to trace on execution of an executable thread thereby indicating to said processor to provide trace information when said executable thread executes; starting execution of said executable thread; and providing an identifier corresponding to said executable thread into said trace memory to indicate that subsequent entries placed into said trace memory are part of said executable thread.
Claim 8
Dependent Claim
24 words
The method as recited in claim 6 wherein providing said identifier uses said trace access instruction to write said identifier into said trace memory.
Claim 9
Dependent Claim
26 words
The method as recited in claim 6 further comprising the processor placing trace information into said trace memory reflecting instruction execution flow in said executable thread.
Claim 10
Dependent Claim
28 words
The method as recited in claim 8 further comprising stopping placing said trace information into said trace memory in response to execution of said executable thread being stopped.
Claim 11
Dependent Claim
35 words
The method as recited in claim 6 further comprising: writing a code associated with said identifier into said trace memory to indicate that data in said trace memory associated with said code is said identifier.
Claim 12
Dependent Claim
37 words
The method as recited in claim 10 wherein a portion of a record in said trace memory is reserved for writing said identifier, write access to said portion of said record requiring a predetermined system privilege level.
Claim 13
Dependent Claim
32 words
The method as recited in claim 6 wherein a debug host provides said processor with said indication to trace on execution of said executable thread, via a debug port on said processor.
Claim 14
Dependent Claim
19 words
The method as recited in claim 6 wherein said executable thread is one of a task and a thread.
Claim 15
Dependent Claim
47 words
The method as recited in claim 1 further comprising: storing trace information into said trace memory prior to said trace access instruction when code is executing at a first privilege level, and stopping storing into said trace memory when code is executed at a second privilege level.
Claim 16
Dependent Claim
27 words
The method as recited in claim 14 wherein said first privilege level is of an application task and said second privilege level being of a system task.
Claim 17
Dependent Claim
19 words
The method as recited in claim 2 wherein said data written into said trace memory is a time stamp.
Claim 18
Dependent Claim
23 words
The method as recited in claim 2 wherein said data written into said trace memory is a state of a hardware peripheral device.
Claim 19
Dependent Claim
74 words
A computer program embodied on computer readable media, for execution on a computer system including a processor, said processor including an on-chip trace memory, and a memory for storing instructions executable by said processor, the computer program comprising: a trace access instruction executable by said processor, to access said trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor.
Claim 20
Dependent Claim
74 words
A computer program embodied on computer readable media, for execution on a computer system including a processor, said processor including an on-chip trace memory, and a memory for storing instructions executable by said processor, the computer program comprising: a trace access instruction executable by said processor, to access said trace memory on said processor, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor.
Claim 21
Dependent Claim
37 words
The computer program as recited in claim 18 wherein said trace access instruction is a write instruction, said write instruction writing data identified by said trace access instruction to one of said locations in said trace memory.
Claim 22
Dependent Claim
60 words
The computer program as in claim 19 further comprising executing a second trace access instruction stored in said memory, and wherein said second trace access instruction is a read instruction, said read instruction reading data from one of said locations in said trace memory, said one location containing data indicative of execution flow of previously executed instructions of said processor.
Claim 23
Dependent Claim
47 words
The computer program as recited in claim 18 wherein said trace access instruction is a read instruction, said read instruction reading data from one of said locations in said trace memory, said one location containing data indicative of execution flow of previously executed instructions of said processor.
Claim 24
Dependent Claim
49 words
The computer program as recited in claim 21 further comprising executing a second trace access instruction stored in said memory and wherein said second trace access instruction is a write instruction writing data identified by said second trace access instruction to one of said locations in said trace memory.
Claim 25
Dependent Claim
72 words
The computer program as recited in claim 18 further comprising: a control segment maintaining a first identifier associated with an executable thread, said executable thread for execution on said processor; a scheduler segment for starting execution of said executable thread; wherein said computer program writes a second identifier, corresponding to said first identifier, into said trace memory to indicate that subsequent entries to said trace memory are part of said executable thread.
Claim 26
Dependent Claim
20 words
The computer program as recited in claim 23 wherein said computer program is a component of a multi-tasking operating system.
Claim 27
Dependent Claim
24 words
The computer program as recited in claim 24 wherein said executable thread is part of an application software program different from said operating system.
Claim 28
Independent Claim
89 words
A method of operating a computer system including a processor and a memory storing instructions for said processor, the method comprising: identifying an executable thread to trace as a first trace condition; in response to said identifying step, storing an indicator that said executable thread is to be traced; providing additional trace control information indicating when to enable tracing instruction execution flow within said executable thread, as a second trace condition; and providing trace information indicating instruction execution flow when said first and second trace conditions are both true.
Claim 29
Independent Claim
89 words
A method of operating a computer system including a processor and a memory storing instructions for said processor, the method comprising: identifying an executable thread to trace as a first trace condition; in response to said identifying step, storing an indicator that said executable thread is to be traced; providing additional trace control information indicating when to enable tracing instruction execution flow within said executable thread, as a second trace condition; and providing trace information indicating instruction execution flow when said first and second trace conditions are both true.
Claim 30
Dependent Claim
22 words
The method as recited in claim 26 wherein said additional trace control information provides an address at which to begin trace operations.
Claim 31
Dependent Claim
23 words
The method as recited in claim 26 wherein said additional trace control information provides a data value at which to begin trace operations.
Claim 32
Dependent Claim
31 words
The method as recited in claim 26 wherein said first and second trace conditions are provided to said processor by a debug host controller via a debug port on said processor.
Claim 33
Dependent Claim
31 words
The method as recited in claim 26 wherein information is written to a trace memory on said processor, said trace memory having a plurality of locations for storing said trace information.
Claim 34
Dependent Claim
102 words
An operating system including a trace handling component, said operating system for execution on a computer system including a processor and memory for storing instructions executable by said processor, the trace handling component comprising: a trace read instruction for accessing an on-chip trace memory on said processor, said trace read instruction being stored in said memory, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor; and a trace write instruction, said trace write instruction writing data identified by said trace write instruction to one of said locations in said trace memory.
Claim 35
Dependent Claim
102 words
An operating system including a trace handling component, said operating system for execution on a computer system including a processor and memory for storing instructions executable by said processor, the trace handling component comprising: a trace read instruction for accessing an on-chip trace memory on said processor, said trace read instruction being stored in said memory, said trace memory having a plurality of locations for storing trace information indicative of instruction execution flow in said processor; and a trace write instruction, said trace write instruction writing data identified by said trace write instruction to one of said locations in said trace memory.
Claim 36
Dependent Claim
76 words
The operating system as recited in claim 31 further comprising: control software maintaining a first identifier associated with one of a task and an executable thread, said executable thread for execution on said processor; scheduler software for starting execution of said executable thread; and wherein said computer program writes a second identifier, corresponding to said first identifier, into said trace memory to indicate that subsequent entries into said trace cache are part of said executable thread.
Claim 37
Dependent Claim
19 words
The operating system as recited in claim 32 wherein said second identifier is the same as said first identifier.
Claim 38
Dependent Claim
31 words
The method as recited in claim 1 wherein said trace access instruction is a write instruction and said write instruction writes data stored in a processor register to said trace memory.
Claim 39
Dependent Claim
35 words
The method as recited in claim 4 wherein said data read from one of said locations in said trace memory is stored into a processor register as a result of execution of said read instruction.
Claim 40
Dependent Claim
30 words
The method as recited in claim 4 wherein said data read from one of said locations in said trace memory is stored in a location determined by said read instruction.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2004-11-05 | 2005-05-07 | 2005-11-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2008-11-05 | 2009-05-07 | 2009-11-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2012-11-05 | 2013-05-07 | 2013-11-06 | $7700.00 | Window Closed / Lapsed |