Data processing apparatus providing bus attribute information for system debugging

Claim 1

A system for compiling an accurate trace of an execution sequence to facilitate debugging, comprising: a first unit requesting an instruction fetch for executing an instruction decode, branch prediction, and precedence branch of a branch instruction; a second unit for calculating operand addresses requesting an operand fetch; a third unit for executing instructions and requesting an operand store; a trace memory for storing a trace of the instructions fetched by said first unit; and a bus control unit connected to said first, second and third units for conducting bus cycles according to an instruction fetch request signal from said first unit, an operand fetch request signal from said second unit, and an operand store request signal from said third unit, wherein said bus control unit outputs a bus attribute signal indicating that an instruction at a destination of a conditional branch instruction has been fetched prior to execution of the conditional branch instruction, and outputs a debug information signal indicating that the conditional branch instruction did not satisfy its branch conditions upon execution of said conditional branch instruction by said third unit, and wherein the trace stored in said trace memory is corrected in accordance with the bus attribute signal and the debug information signal.

Claim 2

A system for compiling an accurate trace of an execution sequence to facilitate debugging, comprising: a first unit requesting an instruction fetch for executing an instruction decode, branch prediction, and precedence branch of a branch instruction; a second unit for calculating operand addresses requesting an operand fetch; a third unit for executing instructions and requesting an operand store; a trace memory for storing a trace of the instructions fetched by said first unit; and a bus control unit connected to said first, second and third units for conducting bus cycles according to an instruction fetch request signal from said first unit, an operand fetch request signal from said second unit, and an operand store request signal from said third unit, wherein said bus control unit outputs a bus attribute signal indicating that an instruction at a destination of a conditional branch instruction has been fetched prior to execution of the conditional branch instruction, and outputs a debug information signal indicating that the conditional branch instruction did not satisfy its branch conditions upon execution of said conditional branch instruction by said third unit, and wherein the trace stored in said trace memory is corrected in accordance with the bus attribute signal and the debug information signal.

Claim 9

A system for compiling an accurate trace of an execution sequence to facilitate debugging, comprising: a data processing circuit including a first unit requesting an instruction fetch for executing an instruction decode, branch prediction, and precedence branch of a branch instruction; a second unit for calculating operand addresses requesting an operand fetch; a third unit for executing instructions and requesting an operand store; a bus control unit connected to said first, second and third units for conducting bus cycles according to an instruction fetch request signal from said first unit, an operand fetch request signal from said second unit, and an operand store request signal from said third unit; and a debug facilitating circuit including bus attribute output means for outputting a bus attribute signal indicating that an instruction at a destination of a conditional branch instruction has been fetched prior to execution of the conditional branch instruction and signal output means for outputting a debug information signal indicating that the conditional branch instruction did not satisfy its branch conditions upon execution of said conditional branch instruction by said third unit, said bus attribute signal and said debug information signal being available external to said data processing unit; a trace memory for storing a trace of the instructions fetched by said first unit; and an incircuit emulator for storing the trace in said trace memory and correcting the trace stored in said trace memory in accordance with the bus attribute signal and the debug information signal supplied thereto.

Claim 10

A system for compiling an accurate trace of an execution sequence to facilitate debugging, comprising: a data processing circuit including a first unit requesting an instruction fetch for executing an instruction decode, branch prediction, and precedence branch of a branch instruction; a second unit for calculating operand addresses requesting an operand fetch; a third unit for executing instructions and requesting an operand store; a bus control unit connected to said first, second and third units for conducting bus cycles according to an instruction fetch request signal from said first unit, an operand fetch request signal from said second unit, and an operand store request signal from said third unit; and a debug facilitating circuit including bus attribute output means for outputting a bus attribute signal indicating that an instruction at a destination of a conditional branch instruction has been fetched prior to execution of the conditional branch instruction and signal output means for outputting a debug information signal indicating that the conditional branch instruction did not satisfy its branch conditions upon execution of said conditional branch instruction by said third unit, said bus attribute signal and said debug information signal being available external to said data processing unit; a trace memory for storing a trace of the instructions fetched by said first unit; and an incircuit emulator for storing the trace in said trace memory and correcting the trace stored in said trace memory in accordance with the bus attribute signal and the debug information signal supplied thereto.