Patent US5863823A successfully refreshed from Google Patents.
US5863823A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Self-aligned edge control in silicon on insulator
Assignee: PSemi Corp
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Filing: 1995-03-21
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Granted: 1999-01-26
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Expires: 2015-03-21
Abstract
Abstract An improved process and structure for channel stop in silicon on insulator using LOCOS isolation are disclosed. Advantages include decreased ion dose requirements; reduced processing time; smaller ΔW characteristics, thus, small transistor size and more precise process control over the edge of a MOSFET. The process also makes possible a wide range of transistor design capabilities and improved transistor operating parameters.
Inventors
- 👤 Mark L. Burgener
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 06:04
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/20; H10P14/29; H10P14/2901; H10P14/2921; H10B; H10B10/00; H10B10/15; H10D; H10D1/00; H10D1/40; H10D1/47; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6713; H10D30/6715; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6744; H10D30/6758; H10D30/6759; H10D86/00; H10D86/201; H10P14/34; H10P14/3402; H10P14/3404; H10P14/3411; H10P14/38; H10P14/3822; H10P90/00; H10P90/19; H10P90/1904; H10P90/1906; H10W; H10W10/00; H10W10/01; H10W10/061; H10W10/10; H10W10/181; H10W10/011; H10W10/012; H10W10/13
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
244 words
A method for isolating an active region of a semiconductor layer from another region of the semiconductor layer comprising the steps of: providing a layer of silicon on an insulating substrate; forming a pad oxide layer on the layer of silicon; providing a layer of silicon nitride on the pad oxide layer; providing a photoresist layer over a portion of the layer of silicon nitride such that the photoresist layer is adapted to define the active region in the silicon layer wherein the active region is adapted for forming a transistor; removing selected portions of the silicon nitride layer as defined by the photoresist layer; removing the photoresist layer to expose a silicon nitride mask that covers portions of the active region; oxidizing portions of the silicon layer as allowed by the silicon nitride mask to form a field oxide such that the silicon layer is oxidized at least in part through to the insulating substrate and such that an edge of the active region extends between the field oxide and the insulating substrate; and implanting ions of a conductivity determining material in the edge of the active region after the portions of the silicon layer have been oxidized such that the ions are blocked by the silicon nitride mask from the portions of the active region that are covered by the silicon nitride mask and such that the ions are self-aligned in the edge of the active region by the silicon nitride mask.
Claim 2
Independent Claim
244 words
A method for isolating an active region of a semiconductor layer from another region of the semiconductor layer comprising the steps of: providing a layer of silicon on an insulating substrate; forming a pad oxide layer on the layer of silicon; providing a layer of silicon nitride on the pad oxide layer; providing a photoresist layer over a portion of the layer of silicon nitride such that the photoresist layer is adapted to define the active region in the silicon layer wherein the active region is adapted for forming a transistor; removing selected portions of the silicon nitride layer as defined by the photoresist layer; removing the photoresist layer to expose a silicon nitride mask that covers portions of the active region; oxidizing portions of the silicon layer as allowed by the silicon nitride mask to form a field oxide such that the silicon layer is oxidized at least in part through to the insulating substrate and such that an edge of the active region extends between the field oxide and the insulating substrate; and implanting ions of a conductivity determining material in the edge of the active region after the portions of the silicon layer have been oxidized such that the ions are blocked by the silicon nitride mask from the portions of the active region that are covered by the silicon nitride mask and such that the ions are self-aligned in the edge of the active region by the silicon nitride mask.
Claim 3
Dependent Claim
36 words
The method of claim 1 wherein the step of providing the layer of silicon on the insulating substrate comprises the step of limiting the layer of silicon to a thickness of about 1,500 Å or less.
Claim 4
Dependent Claim
33 words
The method of claim 1 wherein the step of forming the pad oxide layer comprises the step of limiting the thickness of the pad oxide layer to a range of about 100-150 Å.
Claim 5
Dependent Claim
36 words
The method of claim 1 wherein the step of oxidizing the portions of the silicon layer comprises the step of thermally oxidizing the silicon layer at a temperature in a range of about 900° C.-1000° C.
Claim 6
Dependent Claim
35 words
The method of claim 1 wherein the step of providing a layer of silicon nitride further comprises the step of limiting the thickness of said silicon nitride layer to a range of about 750-2,000 Å.
Claim 7
Dependent Claim
78 words
The method of claim 1 wherein the step of implanting ions of a conductivity determining material further comprises the steps of: providing a second layer of photoresist after the step of oxidizing portions of the silicon but before the step of implanting ions to block the ions of the conductivity determining material from selected regions in the layer of silicon; implanting boron ions into unblocked regions of the field oxide and into the edge of the active region.
Claim 8
Dependent Claim
46 words
The method of claim 6 wherein the step of implanting boron ions further comprises implanting the boron ions having a dosage in a range of about 1×10 14 /cm 2 to 10×10 14 /cm 2 at an implantation energy having a range of about 35-65 keV.
Claim 9
Independent Claim
174 words
A method for making a MOSFET characterized by a small ΔW characteristic comprising the steps of: providing a substrate; providing a semiconductor layer having a thickness of about 1,500 Å or less on the substrate, providing an oxidized layer having a thickness of at least about 100 Å on a portion of the semiconductor layer; providing a silicon nitride layer having a thickness of at least about 750 Å on the oxidized layer; defining an active region for the MOSFET transistor in the semiconductor layer by oxidizing portions of the semiconductor layer where the active region is not desired; oxidizing the semiconductor layer to grow a field oxide through to the substrate at locations not covered by the silicon nitride layer wherein the field oxide is grown such that an edge of the active region extends between the field oxide and the insulating substrate; and implanting ions of a conductivity determining material through the field oxide into the edge of the active region such that the ions are self-aligned by the silicon nitride layer.
Claim 10
Independent Claim
174 words
A method for making a MOSFET characterized by a small ΔW characteristic comprising the steps of: providing a substrate; providing a semiconductor layer having a thickness of about 1,500 Å or less on the substrate, providing an oxidized layer having a thickness of at least about 100 Å on a portion of the semiconductor layer; providing a silicon nitride layer having a thickness of at least about 750 Å on the oxidized layer; defining an active region for the MOSFET transistor in the semiconductor layer by oxidizing portions of the semiconductor layer where the active region is not desired; oxidizing the semiconductor layer to grow a field oxide through to the substrate at locations not covered by the silicon nitride layer wherein the field oxide is grown such that an edge of the active region extends between the field oxide and the insulating substrate; and implanting ions of a conductivity determining material through the field oxide into the edge of the active region such that the ions are self-aligned by the silicon nitride layer.
Claim 11
Dependent Claim
22 words
The method of claim 8 further comprising the step of thinning the field oxide after the step of oxidizing the semiconductor layer.
Claim 12
Dependent Claim
32 words
The method of claim 9 wherein the step of implanting ions of a conductivity determining material includes the step of implanting ions selected from the group consisting of boron, arsenic and phosphorus.
Claim 13
Dependent Claim
49 words
The method of claim 10 wherein the step of implanting ions of a conductivity determining material further comprises the step of implanting boron ions having a dosage in a range of about 1×10 14 cm 2 to 10×10 14 cm 2 at an implant energy of a 35-65 keV.
Claim 14
Independent Claim
157 words
A method for isolating an active region in a semiconductor layer on an insulating substrate wherein the active region is adapted for use in a MOSFET, the method comprising: providing the insulating substrate wherein the substrate has a major surface; providing the semiconductor layer on the major surface of the insulating substrate; providing the active region in the semiconductor layer; providing a nitride mask that covers a portion of the active region and that defines an area of the active region for receiving ions of a conductivity determining material; providing a field oxide adjacent to the defined area of the active region; removing a portion of the field oxide layer; after the step of removing the portion of the field oxide layer, implanting ions from the group consisting of boron, arsenic and phosphorus through the field oxide and into the defined area of the active region such that the implanted ions are self-aligned by the nitride mask.
Claim 15
Independent Claim
157 words
A method for isolating an active region in a semiconductor layer on an insulating substrate wherein the active region is adapted for use in a MOSFET, the method comprising: providing the insulating substrate wherein the substrate has a major surface; providing the semiconductor layer on the major surface of the insulating substrate; providing the active region in the semiconductor layer; providing a nitride mask that covers a portion of the active region and that defines an area of the active region for receiving ions of a conductivity determining material; providing a field oxide adjacent to the defined area of the active region; removing a portion of the field oxide layer; after the step of removing the portion of the field oxide layer, implanting ions from the group consisting of boron, arsenic and phosphorus through the field oxide and into the defined area of the active region such that the implanted ions are self-aligned by the nitride mask.
Claim 16
Dependent Claim
44 words
The method of claim 12 wherein the step of implanting ions further comprises the step of implanting boron ions having a dosage in a range of about 1×10 14 cm 2 to 10×10 14 cm 2 at an implant energy of a 35-65 keV.
Claim 17
Dependent Claim
10 words
The method claim 1 wherein the insulating substrate comprises sapphire.
Claim 18
Dependent Claim
10 words
The method of claim 8, wherein the substrate comprises sapphire.
Claim 19
Dependent Claim
11 words
The method of claim 12 wherein the insulating substrate comprises sapphire.
References Cited (Backward Citations)
US3562425A
Cited
US3829743A
Cited
US3829881A
Cited
US3699544A
Cited
US4065781A
Cited
US4037140A
Cited
US4198649A
Cited
US4183134A
Cited
FR2380637A1
Cited
GB2005073A
Cited
GB2021346A
Cited
US4177084A
Cited
US4282556A
Cited
JPS5690549A
Cited
US4420743A
Cited
US4385937A
Cited
US4425700A
Cited
US4549198A
Cited
JPS57197848A
Cited
US4463492A
Cited
US4418470A
Cited
JPS58222573A
Cited
US4509990A
Cited
US4523963A
Cited
US4876582A
Cited
JPS6074454A
Cited
US5313077A
Cited
US4598305A
Cited
US4588447A
Cited
US4607176A
Cited
JPS61103530A
Cited
US4617066A
Cited
US4659392A
Cited
US4615762A
Cited
US4717836A
Cited
US4843442A
Cited
US4775641A
Cited
US4766482A
Cited
EP0273702A2
Cited
JPS63176145A
Cited
US4851721A
Cited
US5166767A
Cited
US5229644A
Cited
US4872010A
Cited
WO1989007367A2
Cited
US4843448A
Cited
US4989057A
Cited
US4907041A
Cited
US5141882A
Cited
US5027171A
Cited
US5170373A
Cited
US5196802A
Cited
JPH04122020A
Cited
US5294823A
Cited
US5242849A
Cited
JPH0555470A
Cited
US5391903A
Cited
EP0605946A2
Cited
EP0600596A2
Cited
US5445802A
Cited
US5300443A
Cited
US5341009A
Cited
WO1995002892A1
Cited
US5416043A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2002-01-25 | 2002-07-27 | 2003-01-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2006-01-25 | 2006-07-27 | 2007-01-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2010-01-25 | 2010-07-27 | 2011-01-26 | $7700.00 | Window Closed / Lapsed |