Patent US7152215B2 successfully refreshed from Google Patents.
US7152215B2
Expired / Lapsed
US
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Dummy fill for integrated circuits
Assignee: Cadence Design Systems Inc
•
Filing: 2002-06-07
•
Granted: 2006-12-19
•
Expires: 2022-06-07
Abstract
Abstract A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to direct the insertion of dummy fill into an integrated circuit.
Inventors
- 👤 Taber H. Smith
- 👤 Vikas Mehrotra
- 👤 David White
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:07
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/39; H; H10; H10D; H10D89/00; H10D89/10; H10P; H10P52/00; H10P52/40; H10P52/403; H10P95/00; H10P95/06; H10P95/062; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/062; H10W20/071; H10W20/092; G06F2119/00; G06F2119/18; H10W20/40; Y; Y02; Y02P; Y02P90/00; Y02P90/02
Claims Analysis
Total Claims: 83
Claim 1
Independent Claim
154 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the use of the model and dimensional characteristics, and the simulation or analysis of the electrical impact analysis being embedded as part of the generation of the strategy for placing dummy fill features.
Claim 2
Independent Claim
154 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the use of the model and dimensional characteristics, and the simulation or analysis of the electrical impact analysis being embedded as part of the generation of the strategy for placing dummy fill features.
Claim 3
Independent Claim
141 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process floe for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.
Claim 4
Independent Claim
141 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process floe for which the strategy is being generated comprising other than an oxide chemical mechanical polishing process.
Claim 5
Independent Claim
139 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising two or more stages of fabrication.
Claim 6
Independent Claim
139 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising two or more stages of fabrication.
Claim 7
Independent Claim
146 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.
Claim 8
Independent Claim
146 words
A method comprising enabling generation of a strategy for placing dummy fill features within a design of an integrated circuit that is to be fabricated using a fabrication process flow that includes one or more chemical mechanical polishing process steps, the generation of a strategy or the placing of dummy fill features being based on (a) dimensional characteristics of dummy fill and/or non-dummy fill features within the integrated circuit design, (b) predictions by a pattern dependent model characterizing a mapping or interaction between the dimensional characteristics of dummy fill and non-dummy features within the integrated circuit and topography within the integrated circuit, and (c) simulation or analysis of the electrical impact of the dummy fill features on the integrated circuit design, the fabrication process flow for which the strategy is being generated comprising a polishing or planarization process in which more than one material is removed.
Claim 9
Dependent Claim
48 words
The method of claim 1 , 2 , 3 or 4 also including operating a server to provide dummy fill generation functions for a semiconductor design, and enabling a user at a client to operate through a web browser to develop the strategy for placing dummy fill features.
Claim 10
Dependent Claim
14 words
The method of claim 5 in which the server is local to the user.
Claim 11
Dependent Claim
14 words
The method of claim 6 in which the server is remote from the user.
Claim 12
Dependent Claim
58 words
The method of claim 1 , 2 , 3 or 4 also including analyzing a design to which the dummy fill strategy has been applied, adjusting the design based on to analysis, iterating the analyzing and adjusting steps, and certifying that an integrated circuit manufactured according to the adjusted design will be within predefined physical and electrical parameters.
Claim 13
Dependent Claim
15 words
The method of claim 3 in which the two stages comprise two or more processes.
Claim 14
Dependent Claim
19 words
The method of claim 3 in which the two stages comprise two or more steps of a single process.
Claim 15
Dependent Claim
16 words
The method of claim 3 in which the two stages comprise deposition and chemical mechanical polishing.
Claim 16
Dependent Claim
17 words
The method of claim 3 in which the generation of a strategy includes generating dummy fill rules.
Claim 17
Dependent Claim
44 words
The method of claim 1 , 2 , 3 or 4 also including defining a set of hierarchical cell placements for dummy fill, and reducing a size of an electronic layout file to which dummy fill is added by using the hierarchical cell placements.
Claim 18
Dependent Claim
30 words
The method of claim 1 , 2 , 3 or 4 in which the dummy fill generation is performed by a user through a web browser and a web server.
Claim 19
Dependent Claim
15 words
The method of claim 14 in which the web server is local to the user.
Claim 20
Dependent Claim
15 words
The method of claim 14 in which the web server is remote from the user.
Claim 21
Independent Claim
21 words
The method of claims 1 , 2 , 3 or 4 in which the fabrication process flow comprises a damascene process.
Claim 22
Dependent Claim
29 words
The method of claim 1 , 2 , 3 or 4 in which the strategy for placement of dummy fill includes determining the size and placement of dummy fill.
Claim 23
Dependent Claim
24 words
The method of claim 1 , 2 , 3 or 4 in which the fabrication process comprises a formation of a low-K interlayer dielectric.
Claim 24
Dependent Claim
20 words
The method of claim 3 in which the fabrication process comprises chemical vapor deposition or spin-on of the low-K dielectric.
Claim 25
Dependent Claim
25 words
The method of claim 1 , 2 , 3 or 4 in which generating the dummy fill strategy includes dividing a semiconductor design into grids.
Claim 26
Dependent Claim
22 words
The method of claim 21 in which also includes extracting local pattern densities for a semiconductor design for each of the grids.
Claim 27
Dependent Claim
22 words
The method of claim 21 in which also includes extracting local line width for a semiconductor design for each of the grids.
Claim 28
Dependent Claim
22 words
The method of claim 21 in which also includes extracting local line spacing for a semiconductor design for each of the grids.
Claim 29
Dependent Claim
17 words
The method of claim 21 in which also includes computing an effective pattern density for each grid.
Claim 30
Dependent Claim
36 words
The method of claim 22 , 23 , 24 , or 25 also including using models for computing film thickness non-uniformity with respect to a semiconductor design for which the dummy fill strategy is being generated.
Claim 31
Dependent Claim
13 words
The method of claim 26 also including computing a variation in film thickness.
Claim 32
Dependent Claim
17 words
The method of claim 21 also including deriving coordinates of all objects within each of the grids.
Claim 33
Dependent Claim
27 words
The method of claim 28 also including generating at least one of line width, lien space, length, and bounding box with respect to each of the objects.
Claim 34
Dependent Claim
23 words
The method of claim 21 in which the dummy fill strategy includes adding dummy fill in empty areas of each of the grids.
Claim 35
Dependent Claim
14 words
The method of claim 28 in which the dummy fill includes slots in objects.
Claim 36
Dependent Claim
19 words
The method of claim 30 comprising re-computing a local density in each of the grids after adding dummy fill.
Claim 37
Dependent Claim
21 words
The method of claim 30 also comprising re-computing an effective pattern density for each of the grids after adding dummy fill.
Claim 38
Dependent Claim
51 words
The method of claim 1 , 2 , 3 or 4 in which the dummy fill strategy is based on criteria for electrical parameter variation tolerances for at least one of the following; capacitance and resistance, sheet resistance, outputs delay, skew, voltage drop, drive current loss, dielectric constant or crosstalk noise.
Claim 39
Dependent Claim
20 words
The method of claim 33 in which the effective pattern density is computed based on a polishing process planarization length.
Claim 40
Dependent Claim
21 words
The method of claim 33 in which the effective pattern density is computed using an elliptically weighted window or other filter.
Claim 41
Dependent Claim
26 words
The method of claim 11 in which dummy fill rules based on electrical design guidelines are generated dynamically with a change in technology or design parameters.
Claim 42
Dependent Claim
22 words
The method of claim 35 in which an effective pattern density is generated dynamically with a change in a process planarization length.
Claim 43
Dependent Claim
18 words
The method of claim 1 , 2 , 3 or 4 in which the fabrication process comprises lithography.
Claim 44
Dependent Claim
19 words
The method of claim 1 , 2 , 3 or 4 in which the fabrication process comprises electrochemical deposition.
Claim 45
Dependent Claim
21 words
The method of claim 1 , 2 , 3 or 4 in which the fabrication process comprises copper chemical mechanical polishing.
Claim 46
Independent Claim
22 words
The method of claims 1 , 2 , 3 or 4 also including extracting pattern dependencies from a layout of the semiconductor.
Claim 47
Dependent Claim
21 words
The method of claim 42 in which the layout dependencies include with respect to line spacing, line width or line density.
Claim 48
Dependent Claim
59 words
The method of claim 1 , 2 , 3 or 4 also including using patterned test wafers or test semiconductor devices to calibrate a pattern dependent model with respect to a preselected tool or process recipe, and based on a pattern dependent model of a semiconductor fabrication process, generating the strategy for placement of dummy fill in the process.
Claim 49
Dependent Claim
78 words
The method of claim 1 , 2 , 3 or 4 also comprising using a calibrated pattern dependent model to map pattern dependent features to wafer-state parameters such as resulting film thickness, film thickness variation, dishing, erosion and electrical parameters such as sheet resistance, resistance, capacitance, crosstalk noise, drive current loss, voltage drop, dielectric constant and effective dielectric constant, and based on the pattern dependent model, generating the strategy for placement of dummy fill in a fabrication process.
Claim 50
Dependent Claim
52 words
The method of claim 1 , 2 , 3 or 4 also comprising based on a pattern dependent model, generating a strategy for placement of dummy fill in a process, and using a cost function to measure an impact of dummy fill modification on process induced wafer state and electrical parameter variation.
Claim 51
Dependent Claim
50 words
The method of claim 1 , 2 , 3 or 4 also comprising based on a combination of more than one pattern dependent model, generating a strategy for placement of dummy fill in a process, and predicting an impact of the dummy fill generated by the strategy on process variation.
Claim 52
Dependent Claim
45 words
The method of claim 1 , 2 , 3 or 4 also comprising based on a combination of more than one pattern dependent model and cost function, generating a strategy for placement of dummy fill in a process that optimizes full-chip wafer-state and electrical parameters.
Claim 53
Dependent Claim
38 words
The method of claim 1 , 2 , 3 or 4 also comprising based on predicted or simulated wafer state and electrical parameters, generating dummy fill rules for use in dummy fill placement in a semiconductor fabrication process.
Claim 54
Dependent Claim
15 words
The method of claim 49 in which the dummy fill rules include dummy fill sizing.
Claim 55
Dependent Claim
15 words
The method of claim 49 in which the dummy fill rules include dummy fill placement.
Claim 56
Dependent Claim
19 words
The method of claim 49 in which the dummy fill rules include dummy fill hierarchical cell creation and management.
Claim 57
Dependent Claim
38 words
The method of claim 1 , 2 , 3 or 4 also comprising providing dummy fill functions to generate the dummy fill strategy, and using the functions to automatically modify GDS-format electronic layout files for a semiconductor device.
Claim 58
Dependent Claim
53 words
The method of claim 1 , 2 , 3 or 4 also comprising at an internet server, receiving from a client a layout file for a semiconductor device, generating dummy fill modifications to the layout file at the server, and returning the dummy fill modified layout file from the server to the client.
Claim 59
Dependent Claim
48 words
The method of claim 1 , 2 , 3 or 4 also comprising at a server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and enabling the user to generate dummy fill information using the dummy fill application.
Claim 60
Dependent Claim
42 words
The method of claim 1 , 2 , 3 or 4 also comprising making available to a user on a network a service that enables the user to verify dummy fill information with respect to a semiconductor design and a fabrication process.
Claim 61
Dependent Claim
32 words
The method of claim 56 in which the dummy fill information that is verified includes at least one of a dummy fill pattern, a dummy fill strategy, or a dummy fill representation.
Claim 62
Dependent Claim
24 words
The method of claim 56 in which the dummy fill information is verified with respect to a single interconnect level of the semiconductor design.
Claim 63
Dependent Claim
23 words
The method of claim 56 in which the dummy fill information is verified with respect to multiple interconnect levels of the semiconductor design.
Claim 64
Dependent Claim
30 words
The method of claim 56 also including sizing dummy fill objects and creating a dummy fill pattern of the objects for one or more interconnect levels of the semiconductor design.
Claim 65
Dependent Claim
15 words
The method of claim 56 in which the dummy fill information comprises dummy fill rules.
Claim 66
Dependent Claim
16 words
The method of claim 60 in which the pattern includes oxide or metal dummy fill objects.
Claim 67
Dependent Claim
22 words
The method of claim 60 in which the objects of the dummy fill pattern are placed to minimize full-chip film thickness variation.
Claim 68
Dependent Claim
23 words
The method of claim 60 in which the objects of the dummy fill pattern are placed to minimize full-chip variation in electrical parameters.
Claim 69
Dependent Claim
30 words
The method of claim 64 in which the electrical parameters comprise at least one of sheet resistance, resistance, capacitance, crosstalk noise, voltage drop, drive current loss, and effective dielectric constant.
Claim 70
Dependent Claim
22 words
The method of claim 53 in which the GDS files are modified to improve uniformity and electrical performance of the semiconductor device.
Claim 71
Dependent Claim
13 words
The method of claim 66 in which the process comprises damascene process flow.
Claim 72
Dependent Claim
15 words
The method of claim 56 where the network is an intranet, extranet or the internet.
Claim 73
Dependent Claim
49 words
The method of claim 1 , 2 , 3 or 4 also comprising at a web server, providing a service that enables a user to interactively configure a dummy fill application running on the server, and enabling the user to generate dummy fill information using the dummy fill application.
Claim 74
Dependent Claim
32 words
The method of claim 1 , 2 , 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to improve a structural integrity of low-K dielectric features.
Claim 75
Dependent Claim
35 words
The method of claim 1 , 2 , 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to maintain or improve an effective dielectric constant of low-K dielectric features.
Claim 76
Dependent Claim
23 words
The method of claim 60 or 71 in which the effective dielectric constant is maintained through all steps of a damascene process flow.
Claim 77
Dependent Claim
33 words
The method of claim 1 , 2 , 3 or 4 in which the dummy fill placement strategy includes using dummy fill objects to facilitate integration of low-k dielectric materials into-damascene process flow.
Claim 78
Dependent Claim
45 words
The method of claim 1 , 2 , 3 or 4 also comprising maintaining a library of semiconductor dummy fill information, and making the library available for use in connection with generating dummy fill placement specifications, and updating the library with changed dummy fill information.
Claim 79
Dependent Claim
45 words
The method of claim 1 , 2 , 3 or 4 also comprising storing calibration information with respect to at least one of the following: process tools, recipes, and flows, and updating the calibration information to reflect changes in the process tools, recipes or flows.
Claim 80
Dependent Claim
17 words
The method of claim 72 also including using the calibration information in generating a dummy fill strategy.
Claim 81
Dependent Claim
23 words
The method of claim 72 also including selecting among process tools, recipes and flows from calibration database based upon desired dummy fill characteristics.
Claim 82
Dependent Claim
39 words
The method of claim 1 , 2 , 3 or 4 also comprising enabling a user to obtain a dummy fill strategy for a semiconductor design using a single click of a user interface device through a user interface.
Claim 83
Dependent Claim
32 words
The method of claim 1 , 2 , 3 or 4 also comprising enabling a user to obtain a dummy fill strategy for a semiconductor design over the internet using web services.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 2009-12-18 | 2010-06-19 | 2010-12-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2013-12-18 | 2014-06-19 | 2014-12-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2017-12-18 | 2018-06-19 | 2018-12-19 | $7700.00 | Window Closed / Lapsed |