US5796623A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus and method for performing computations with electrically reconfigurable logic devices
Assignee: Quickturn Design Systems Inc
•
Filing: 1996-12-19
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Granted: 1998-08-18
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Expires: 2016-12-19
Abstract
Abstract A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.
Inventors
- 👤 Michael R. Butts
- 👤 Jon A. Batcheller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 18:58
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33; G06F30/3308; G06F30/331; G06F30/34; G06F30/347; G06F30/39
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
197 words
An apparatus for performing computations comprising: a compiler that converts a computer program comprising a sequence of instructions into input data representative of a digital logic network; a partitioner which partitions said input data into at least a first partition and a second partition; a first electrically reconfigurable device, said first electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said first electrically reconfigurable device capable receiving said first partition so that a first portion of said digital logic network can take actual operating form in said first electrically reconfigurable device; a second electrically reconfigurable device, said second electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said second electrically reconfigurable device capable receiving said second partition so that a second portion of said digital logic network can take actual operating form in said second electrically reconfigurable device; and at least one electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of said first and said second electrically reconfigurable devices.
Claim 2
Independent Claim
197 words
An apparatus for performing computations comprising: a compiler that converts a computer program comprising a sequence of instructions into input data representative of a digital logic network; a partitioner which partitions said input data into at least a first partition and a second partition; a first electrically reconfigurable device, said first electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said first electrically reconfigurable device capable receiving said first partition so that a first portion of said digital logic network can take actual operating form in said first electrically reconfigurable device; a second electrically reconfigurable device, said second electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, said second electrically reconfigurable device capable receiving said second partition so that a second portion of said digital logic network can take actual operating form in said second electrically reconfigurable device; and at least one electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of said first and said second electrically reconfigurable devices.
Claim 3
Independent Claim
186 words
An apparatus for performing computations comprising: a compiler that converts a computer program comprising a sequence of instructions into input data representative of a digital logic network; a partitioner which partitions said input data into at least two partitions; a plurality of electrically reconfigurable devices, said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, a first of said plurality of electrically reconfigurable devices capable receiving a first of said at least two partitions so that a first portion of said digital logic network can take actual operating form in said first of said plurality of electrically reconfigurable devices, a second of said plurality of electrically reconfigurable devices capable receiving a second of said at least two partitions so that a second portion of said digital logic network can take actual operating form in said second of said plurality of electrically reconfigurable devices; at least one electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of said plurality of electrically reconfigurable devices.
Claim 4
Independent Claim
186 words
An apparatus for performing computations comprising: a compiler that converts a computer program comprising a sequence of instructions into input data representative of a digital logic network; a partitioner which partitions said input data into at least two partitions; a plurality of electrically reconfigurable devices, said plurality of electrically reconfigurable devices containing reprogrammable functional logic elements and input/output terminals capable of being connected to at least some of said functional logic elements, a first of said plurality of electrically reconfigurable devices capable receiving a first of said at least two partitions so that a first portion of said digital logic network can take actual operating form in said first of said plurality of electrically reconfigurable devices, a second of said plurality of electrically reconfigurable devices capable receiving a second of said at least two partitions so that a second portion of said digital logic network can take actual operating form in said second of said plurality of electrically reconfigurable devices; at least one electrically reconfigurable device containing reprogrammable electrical conductors which are used to reconfigurably interconnect selected input/output terminals of said plurality of electrically reconfigurable devices.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-08-17 | 2002-02-16 | 2002-08-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-08-17 | 2006-02-16 | 2006-08-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-08-17 | 2010-02-16 | 2010-08-18 | $7700.00 | Window Closed / Lapsed |