Patent US5754871A successfully refreshed from Google Patents.
US5754871A
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Parallel processing system having asynchronous SIMD processing
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1998-05-19
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Expires: 2015-06-07
Abstract
Abstract A parallel array processor for massively parallel applications is formed with low power CMOS with DRAM processing while incorporating processing elements on a single chip. Eight processors on a single chip have their own associated processing element, significant memory, and I/O and are interconnected with a hypercube based, but modified, topology. These nodes are then interconnected, either by a hypercube, modified hypercube, ring, or ring within ring network topology. Conventional microprocessor MMPs consume pins and time going to memory. The new architecture merges processor and memory with multiple PMEs (eight 16 bit processors with 32K and I/O) in DRAM and has no memory access delays and uses all the pins for networking. The chip can be a single node of a fine-grained parallel processor. Each chip will have eight 16 bit processors, each processor providing 5 MIPs performance. I/O has three internal ports and one external port shared by the plural processors on the chip. The scalable chip PME has internal and external connections for broadcast and asynchronous SIMD, MIMD and SIMIMD (SIMD/MIMD) with dynamic switching of modes. The chip can be used in systems which employ 32, 64 or 128,000 processors. Local and global memory functions can all be provided by the chips themselves, and the system can connect to and support other global memories and DASD. The chip can be used as a microprocessor accelerator, in personal computer applications, as a vision or avionics computer system, or as workstation or supercomputer.
Inventors
- 👤 Paul Amba Wilkinson
- 👤 James Warren Dieffenderfer
- 👤 Peter Michael Kogge
- 👤 Nicholas Jerome Schoonover
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:02
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/80; G06F15/8007; G06F15/8015; G06F15/803; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/30038; G06F9/30145; G06F9/3016; G06F9/30167; G06F9/3017; G06F9/30181; G06F9/30189; G06F9/3802; G06F9/3824; G06F9/3834; G06F9/3836; G06F9/3838; G06F9/3851; G06F9/3887; G06F9/3888; G06F9/3889; G06F9/3891
Claims Analysis
Total Claims: 34
Claim 1
Independent Claim
262 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the processing elements are primarily adapted for use as a SIMD machine for SIMD architecture.
Claim 2
Dependent Claim
262 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the processing elements are primarily adapted for use as a SIMD machine for SIMD architecture.
Claim 3
Dependent Claim
262 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the processing elements are physical MIND processing elements, and emulate operation as a SIMD architecture.
Claim 4
Dependent Claim
262 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the processing elements are physical MIND processing elements, and emulate operation as a SIMD architecture.
Claim 5
Dependent Claim
270 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor and the processing elements include a control structure for emulating SIMD operation with the processing elements having individual instruction streams.
Claim 6
Dependent Claim
270 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor and the processing elements include a control structure for emulating SIMD operation with the processing elements having individual instruction streams.
Claim 7
Dependent Claim
277 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor and the processing elements include a control structure for emulating SIMD operation with the processing elements having individual instructions streams and with a fine grained array design.
Claim 8
Dependent Claim
277 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor and the processing elements include a control structure for emulating SIMD operation with the processing elements having individual instructions streams and with a fine grained array design.
Claim 9
Dependent Claim
279 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and further comprising an interconnection network formed by said plurality of processing elements interconnected as an array processor, wherein the control processor is cooperative with said interconnection network to execute reduction and related operations.
Claim 10
Dependent Claim
279 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and further comprising an interconnection network formed by said plurality of processing elements interconnected as an array processor, wherein the control processor is cooperative with said interconnection network to execute reduction and related operations.
Claim 11
Dependent Claim
310 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the system provides a SIMIMD mode wherein each respective memory of the processor elements include respective small amounts of program code which is executed by each respective processing element on multiple independent data streams located one per processing element on multiple independent data streams located one per processing element in response to single instructions broadcast from the control processor to the processing elements.
Claim 12
Dependent Claim
310 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the system provides a SIMIMD mode wherein each respective memory of the processor elements include respective small amounts of program code which is executed by each respective processing element on multiple independent data streams located one per processing element on multiple independent data streams located one per processing element in response to single instructions broadcast from the control processor to the processing elements.
Claim 13
Dependent Claim
34 words
An array processing system according to claim 6 wherein control is retained by the control processor, after which additional small amounts of code may be loaded into each of the processing elements and executed.
Claim 14
Dependent Claim
406 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIND mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and including a partition manager to load identical code onto every processing node in a partition of processing elements selected from among the plurality of processing elements, in the array processing system, wherein data is distributed across the processing elements in the partition, and giving an array of m values of data and a partition of n nodes, where ma and n are integers, each processing element in the partition is assigned to m/n distinct elements of the array, and wherein each processing element in the partition selectively executes the code independently, branching according to its own data values, and wherein while computation remains local within each processing element of the partition, no synchronization or communication is needed, and wherein when data needs to be transferred among processor elements, including during execution of global operations, a communication network communicates the dat and enforces the necessary synchronization, and during execution of global combining operations the control processor functions to perform the reduction.
Claim 15
Dependent Claim
406 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIND mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and including a partition manager to load identical code onto every processing node in a partition of processing elements selected from among the plurality of processing elements, in the array processing system, wherein data is distributed across the processing elements in the partition, and giving an array of m values of data and a partition of n nodes, where ma and n are integers, each processing element in the partition is assigned to m/n distinct elements of the array, and wherein each processing element in the partition selectively executes the code independently, branching according to its own data values, and wherein while computation remains local within each processing element of the partition, no synchronization or communication is needed, and wherein when data needs to be transferred among processor elements, including during execution of global operations, a communication network communicates the dat and enforces the necessary synchronization, and during execution of global combining operations the control processor functions to perform the reduction.
Claim 16
Dependent Claim
343 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein said control processor broadcasts a first signal to said processing elements to enter a synchronous mode, and wherein each of said processing elements individually responds to said first signal at a time when it is ready for synchronous operation by communicating an acknowledgement signal to the control processor indicating that it is ready for synchronous operation; and wherein processing elements that have responded to said first signal selectively operating in MIMD mode for execution of unrelated processing within a waiting time period ending after all processing elements respond to said first signal from the control processor.
Claim 17
Dependent Claim
343 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein said control processor broadcasts a first signal to said processing elements to enter a synchronous mode, and wherein each of said processing elements individually responds to said first signal at a time when it is ready for synchronous operation by communicating an acknowledgement signal to the control processor indicating that it is ready for synchronous operation; and wherein processing elements that have responded to said first signal selectively operating in MIMD mode for execution of unrelated processing within a waiting time period ending after all processing elements respond to said first signal from the control processor.
Claim 18
Dependent Claim
285 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein at least one of said processing elements does not have an entire operating system stored in its respective memory, and said controler downloads or broadcasts code, along with data to said at least one of said processing elements.
Claim 19
Dependent Claim
285 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein at least one of said processing elements does not have an entire operating system stored in its respective memory, and said controler downloads or broadcasts code, along with data to said at least one of said processing elements.
Claim 20
Dependent Claim
302 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor broadcasts an instruction code to at least one or more of said processing elements, and each respective processor of the at least one of said processing elements executes the instruction code by operating on data stored in the memory respectively coupled thereto and executing computations and branches according to the instruction code.
Claim 21
Dependent Claim
302 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the control processor broadcasts an instruction code to at least one or more of said processing elements, and each respective processor of the at least one of said processing elements executes the instruction code by operating on data stored in the memory respectively coupled thereto and executing computations and branches according to the instruction code.
Claim 22
Dependent Claim
301 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each processor of a group of said plurality of processing elements selectively fetches from a common address in the respective memories to executes SIMD-mode in a given individual instruction of the single instruction stream, or from an address selected independently of said group of said plurality of processing elements to execute independent MIMD-mode instructions.
Claim 23
Dependent Claim
301 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each processor of a group of said plurality of processing elements selectively fetches from a common address in the respective memories to executes SIMD-mode in a given individual instruction of the single instruction stream, or from an address selected independently of said group of said plurality of processing elements to execute independent MIMD-mode instructions.
Claim 24
Dependent Claim
273 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each of the processing elements is a VLSI chip RISC processor system wherein each said memory includes both local and global memory at each processing element.
Claim 25
Dependent Claim
273 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each of the processing elements is a VLSI chip RISC processor system wherein each said memory includes both local and global memory at each processing element.
Claim 26
Dependent Claim
269 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein a processing element during execution of a program is enabled to load a portion of an application code into its own memory.
Claim 27
Dependent Claim
269 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein a processing element during execution of a program is enabled to load a portion of an application code into its own memory.
Claim 28
Dependent Claim
43 words
A computer system according to claim 14, wherein a processing element during execution of a program is enabled to load a portion of an application code into its own memory and wherein execution includes execution of runtime code supplied by a library function.
Claim 29
Dependent Claim
267 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the system supports data parallel coding and wherein each of said plurality of processing elements selectively executes branching and synchronization.
Claim 30
Dependent Claim
267 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein the system supports data parallel coding and wherein each of said plurality of processing elements selectively executes branching and synchronization.
Claim 31
Dependent Claim
313 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each said processor of said plurality of processing elements selectively fetches from a respective addressable location of its respective memory having a common address, corresponding to operation in a SIMD mode, or fetches from a respective addressable location of its respective memory having an address selected independently of other ones of said plurality of processing elements individually chosen addresses, corresponding to operation in said MIMD mode.
Claim 32
Dependent Claim
313 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIMD mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each said processor of said plurality of processing elements selectively fetches from a respective addressable location of its respective memory having a common address, corresponding to operation in a SIMD mode, or fetches from a respective addressable location of its respective memory having an address selected independently of other ones of said plurality of processing elements individually chosen addresses, corresponding to operation in said MIMD mode.
Claim 33
Dependent Claim
291 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIND mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each said memory of each respective said processing element contains addressable storage locations, wherein the addressable storage locations of each said memory are locally addressable by the processor coupled thereto, and are globally addressable by each other processor of the plurality of processing elements.
Claim 34
Dependent Claim
291 words
An array processing system, comprising: a plurality of processing elements interconnected as an array processor, each having a processor and a memory coupled to said processor, and wherein each of the processing elements selectively and automatically executes an independent instruction stream on an independent multiple data stream, thereby providing for an MIND mode; a control processor that dispatches a series of single instructions to the plurality of processing elements, each of the single instructions operative to command the respective processing elements to execute respective multiple independent instruction streams on multiple independent data streams located one per processing element, each successive instruction of said single instructions being dispatched by said control processor in response to all of said processing elements accessing an instruction immediately preceding said each successive instruction; wherein a first one of said processing elements which has completed execution of a multiple instruction stream in response to an instruction of said single instructions accesses and begins executing an immediately subsequent instruction of said single instructions after all other processing elements have read said instruction and before all other processing elements complete execution of respective multiple instruction streams in response to said instruction, whereby the processing elements execute the series of single instructions independently of a fixed time relationship between or among the processing elements with respect to accessing a subsequent single instruction before all processing elements have completed executing multiple instructions in response to a single instruction immediately precedent to said subsequent single instruction; and wherein each said memory of each respective said processing element contains addressable storage locations, wherein the addressable storage locations of each said memory are locally addressable by the processor coupled thereto, and are globally addressable by each other processor of the plurality of processing elements.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2001-05-18 | 2001-11-17 | 2002-05-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2005-05-18 | 2005-11-17 | 2006-05-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2009-05-18 | 2009-11-17 | 2010-05-19 | $7700.00 | Window Closed / Lapsed |