Parallel processor

Claim 2

A parallel processor array according to claim 1 in which each processor/memory includes data generation means (280,287) for selectively generating messages, each including an address and data.

Claim 3

A parallel processor array according to claims 1 or 2 in which said data generation means (280) includes an arithmetic and logic unit (280) for generating a sum signal and a carry signal, said carry signal constituting the data generated by the respective processor.

Claim 4

A parallel processor array according to claim 3 in which each arithmetic and logic unit includes: A. a decoder (282) that receives input signals from a memory and from a flag controller and generates an output signal on one of a plurality of output lines in response thereto; B. a sum selector circuit (284) connected to the output lines of said decoder and further connected to receive sum instruction signals for generating said sum signal in response thereto; and C. a carry selector circuit (286) connected to the output lines of said decoder and further connected to receive carry instruction signals for generating said carry signal in response thereto.

Claim 5

A parallel processor array according to claims 3 or 4 in which said processor/memories receive sum instruction signals (284,162) and carry instruction signals (286,164) in parallel.

Claim 6

A parallel processor array according to at least one of the claims 1 to 5 in which said first communications network includes a plurality of transmission gates (287), each connected to the data generation means of said processor/memories for enabling the processor/memories to transmit data generated by the processor/memories, a plurality of receiving gates for receiving data from transmission gates of adjacent processor/memories.

Claim 7

A parallel processor array according to at least one of the preceding claims in which each interconnection node is connected over a plurality of communications links to other nodes to form said second communications network, each said address in each message has a plurality of address digits, each address digit having a link selection condition or a link non-selection condition and being associated with one of said communications links, each said node comprising: A. a receiver (38) for receiving messages from the plurality of communications links connected to said node, the receiver of at least some of said nodes further receiving messages from at least one processor/memory; B. a communications link association circuit (200) for determining the condition of at least some of the address digits of the messages received by said receiver and for associating one of said communications links therewith in response to the address digit associated with that communications link having a link selection condition; and C. a message transmission circuit (39) for transmitting the message over the associated communications link as determined by said communications link association circuit.

Claim 8

A parallel processor array according to claim 7 in which said message transmission circuit (415) complements the address digit associated with the communications link over which the message is being transmitted.

Claim 9

A parallel processor array according to claims 7 or 8 further comprising a message store (215) connected to said communications link association circuit, said communications link association circuit determining whether a plurality of contemporaneously-received messages are associated with a single communications link and, if so, coupling at least one to said message store, said message store thereafter transferring the stored message back to said communications link association circuit.

Claim 10

A parallel processor array according to claims 7 to 9 wherein said node further includes a message extractor (210) connected to said communications link association circuit and said processor/memories, and further wherein said communications link association circuit may determine that the message is associated with none of the communications links, said communications link association circuit transferring those messages which it determines are associated with none of the communications links to said message extractor, and said message extractor receiving those messages directed to it by the communications link association circuit and coupling them to a processor/memory connected thereto.

Claim 11

A parallel processor array according to at least one of the preceding claims further including a control circuit (10,20) for generating control signals for controlling said processor/memories in parallel, said interconnection nodes in parallel, and said first communications network in parallel.