US4338675A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Numeric data processor
Assignee: Intel Corp
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Filing: 1980-02-13
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Granted: 1982-07-06
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Expires: 2000-02-13
Abstract
Abstract A floating point, integrated, arithmetic circuit is organized around a file format having a floating point numeric domain exceeding that of any single or double precision floating point numbers, long or short integer words or BCD data upon which it must operate. As a result the circuit has a greater reliability, range and precision than ever previously achieved without entailing additional circuit complexity. Reliability is further enhanced by a systematic three bit rounding field, and by including means for detecting every error or exception condition with an optional expected response provided thereto by hardware. As a result of such organization, an unexpected increase of capacity is achieved wherein transcendental functions can be computed totally in hardware, and whereby mixed mode arithmetic can be implemented without difficulty. The numeric processor also includes a programmable shifter capable of arbitrary numbers of bit and byte shifts in a single clock cycle, as well as an arithmetic unit capable of implementing multiplication, division, modulo reduction and square roots directly in hardware.
Inventors
- 👤 John F. Palmer
- 👤 Bruce W. Ravenel
- 👤 Rafi Nave
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 21:29
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3861; G06F11/00; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763; G06F5/00; G06F5/01; G06F5/012; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F7/544; G06F7/552; G06F7/5525; G06F7/60; G06F7/72; G06F9/3877; G06F7/499; G06F7/49905; G06F7/4991; G06F7/49942; G06F7/49947; G06F7/49957; G06F7/49963
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
183 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; and means for rounding said numeric information in a selected one of a plurality of modes, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the Or-function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round bits.
Claim 2
Dependent Claim
183 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; and means for rounding said numeric information in a selected one of a plurality of modes, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the Or-function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round bits.
Claim 3
Dependent Claim
134 words
An improvement in a numeric data processor for performing calculations on numeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means; means for rounding said numeric quantities in a selected one of a plurality of modes, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to said numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from one of said numeric quantities.
Claim 4
Dependent Claim
134 words
An improvement in a numeric data processor for performing calculations on numeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means; means for rounding said numeric quantities in a selected one of a plurality of modes, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to said numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from one of said numeric quantities.
Claim 5
Dependent Claim
175 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to a fraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; and rounding said numeric quantities in one of a plurality of modes by means for rounding, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round bits.
Claim 6
Dependent Claim
175 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to a fraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; and rounding said numeric quantities in one of a plurality of modes by means for rounding, wherein said means for rounding includes a three bit register for storing a guard, round and sticky bit corresponding to a numeric quantity, said sticky bit being the exclusive-or function of all right shifted bits from said numeric quantity beyond the bit location of said guard and round bits.
Claim 7
Dependent Claim
73 words
An improvement in a method for calculating numeric quantities comprising the steps of: detecting every numeric exceptions during computational operations in a numeric processor; indicating the nature of said exceptions detected in a status register; generating a response in hardware within said numeric processor specific to the indicated exception without generating an interrupt signal, including the exception of operations employing and resulting in signed zeros and infinity; and selectively masking said generated response.
Claim 8
Dependent Claim
73 words
An improvement in a method for calculating numeric quantities comprising the steps of: detecting every numeric exceptions during computational operations in a numeric processor; indicating the nature of said exceptions detected in a status register; generating a response in hardware within said numeric processor specific to the indicated exception without generating an interrupt signal, including the exception of operations employing and resulting in signed zeros and infinity; and selectively masking said generated response.
Claim 9
Dependent Claim
203 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; means for rounding said numeric information in a selected one of a plurality of modes; and means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding, whereby reliability of calculation is increased.
Claim 10
Dependent Claim
203 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; means for rounding said numeric information in a selected one of a plurality of modes; and means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding, whereby reliability of calculation is increased.
Claim 11
Dependent Claim
184 words
An improvement in a numeric data processor for performing calculations on mumeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means; means for rounding said numeric quantities in a selected one of a plurality of modes; and means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding, whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 12
Dependent Claim
184 words
An improvement in a numeric data processor for performing calculations on mumeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said numeric quantities wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; third means for selectively providing a specific response to each said exception when said exception is masked, said third means being coupled to said second and first means; means for rounding said numeric quantities in a selected one of a plurality of modes; and means for performing exact arithmetic including a P flag register and PM mask register, wherein said P flag register is set if rounding occurs within said means for rounding and an interrupt is generated by an interrupt means, and wherein if said PM mask register is set, execution continues without interrupt generation with a rounded result generated by said means for rounding, whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 13
Dependent Claim
151 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to afraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; rounding said numeric quantities in one of a plurality of modes by a means for rounding; selectively setting a P flag register if rounding occurs; and generating an interrupt if a PM mask register is not set, otherwise generating a rounded result.
Claim 14
Dependent Claim
151 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to afraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; rounding said numeric quantities in one of a plurality of modes by a means for rounding; selectively setting a P flag register if rounding occurs; and generating an interrupt if a PM mask register is not set, otherwise generating a rounded result.
Claim 15
Dependent Claim
213 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; second means for detecting and indicating numeric exceptions during computational operation and handling of said information; third means for selectively masking a response to said numeric exceptions; and fourth means for selectively providing a specific response in hardware and without the generations of an interrupt signal to each said exception when said exception is masked, said fourth means being coupled to said second and third means, whereby every exception during numeric processing is detected and indicated, and, if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 16
Dependent Claim
213 words
An improvement in a numeric data processor for performing calculations on a plurality of data formats representable by a fraction and exponent representation comprising: first means for converting said plurality of data formats to a file format having a fraction and exponent representation wherein said file format has a numeric fraction and exponent domain greater than any one of said plurality of data formats; a fraction and exponent bus coupled to said first means; a stack of registers configured to store numeric information in said file format, said stack coupled to said exponent and fraction bus; an arithmetic unit to perform arithmetic operations on said information in said file format, said arithmetic unit being coupled to said fraction bus; second means for detecting and indicating numeric exceptions during computational operation and handling of said information; third means for selectively masking a response to said numeric exceptions; and fourth means for selectively providing a specific response in hardware and without the generations of an interrupt signal to each said exception when said exception is masked, said fourth means being coupled to said second and third means, whereby every exception during numeric processing is detected and indicated, and, if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 17
Dependent Claim
105 words
An improvement in a numeric data processor for performing calculations on numeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said information wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; and third means for selectively providing a specific response in hardware and without generating an interrupt signal, said third means being coupled to said second and first means, whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 18
Dependent Claim
105 words
An improvement in a numeric data processor for performing calculations on numeric quantities comprising: first means for detecting and indicating numeric exceptions during computational operation and handling of said information wherein said exceptions include signed zeros and infinity; second means for selectively masking a response to said numeric exceptions; and third means for selectively providing a specific response in hardware and without generating an interrupt signal, said third means being coupled to said second and first means, whereby every exception during numeric processing is detected and indicated and if masked, will be provided with a response so that calculation may proceed in a reliable manner.
Claim 19
Dependent Claim
181 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to a fraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; reconverting a file format numeric quantity in said stack of registers by said conversion means into a selected one of said plurality of data formats; detecting and indicating numeric exceptions during said steps of converting, reconverting, performing arithmetic operations in an error detection means; and selectively providing a specific response to each said exception in hardware without generating an interrupt signal when said exception is masked by an error handling means.
Claim 20
Dependent Claim
181 words
An improvement in a method for calculating numeric quantities having a plurality of data formats representable by a fraction and exponent representation in a numeric processor comprising the steps of: converting said plurality of data formats to a file format in a conversion means wherein said file format has an exponent and fraction numeric domain greater than any one of said plurality of data formats; storing said converted data format in file format within a stack of registers; selectively coupling said file format numeric quantities to a fraction and exponent bus; selectively coupling said file format numeric quantities to an arithmetic unit and performing arithmetic operations in file format thereon; reconverting a file format numeric quantity in said stack of registers by said conversion means into a selected one of said plurality of data formats; detecting and indicating numeric exceptions during said steps of converting, reconverting, performing arithmetic operations in an error detection means; and selectively providing a specific response to each said exception in hardware without generating an interrupt signal when said exception is masked by an error handling means.
References Cited (Backward Citations)
US3434114A
Cited
US3594565A
Cited
US3603934A
Cited
US3905025A
Cited
US3871578A
Cited
US4021655A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-07-05 | 1986-01-04 | 1986-07-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-07-05 | 1990-01-04 | 1990-07-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-07-05 | 1994-01-04 | 1994-07-06 | $7700.00 | Window Closed / Lapsed |