US4964032A
Expired / Lapsed
US
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Minimal connectivity parallel data processing system
Assignee: INTELLECTUAL PROPERTY DEVELOPMENT ASSOCIATES OF CONNECTICUT Inc
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Filing: 1988-11-14
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Granted: 1990-10-16
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Expires: 2008-11-14
Abstract
Abstract A parallel data processing system comprises a control data processor and a plurality of processing planes, each of the planes comprising a plurality of data processing cells. Each of the cells within a plane is communicatively coupled to adjacent, coplanarly disposed cells and, in addition, is communicatively coupled to a corrresponding cell disposed in an overlying processing plane and to a corresponding cell disposed in an underlying processing plane. The control data processor is coupled to each of the cells within a given plane in a manner which provides for simultaneous communication with each of the cells within the plane. Each of the cells within a plane is provided with an output status signal operable for being combined with the output status signals from other cells within the plane to provide an input signal to the control data processor. The status signal may be expressive, when asserted, of a processing state common to all of the cells within the plane, thereby facilitating the operation of the control data processor in controlling a flow of data between adjacent processing planes, in initiating a desired processing sequence within a given plane, and in assuring the reception of data transmitted to the cells.
Inventors
- 👤 Harry F. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 19:24
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F15/803; G06F15/8023; G06N; G06N3/00; G06N3/02; G06N3/10
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
318 words
In a parallel data processing system comprised of at least a two dimensional array of data processing cells, each of the cells comprising a plurality of input and output communication signal lines for electrically coupling to at least all immediately neighboring cells, at least one cell disposed at a unique position at an edge of the array having input communication signal lines coupled to a predetermined logic state, a method of determining by the control data processor that at least one of the cells of the array is inoperable, the method comprising the steps of: initially resetting the cells of the array to a common processing state; determining by each of the cells a position of the cell within the array, the step of determining a position including the steps of: initiating an input signal line logic state determination processing state within all of the cells of the array; detecting, by the at least one cell at the edge of the array, the predetermined logic state; determining from the detected predetermined logic state that the cell is located at the unique position within the array; communicating the position of the cell to at least one other neighboring cell whereby the cell so communicated to is enabled to determine its position within the array relative to the unique position of the cell disposed at the edge of the array, each of the cells within the array communicating its relative position to at least one neighboring cell until each of the cells within the array has determined its position relative to the unique position; the method further comprising the steps of: transmitting the position of at least one cell to the control data processor; comparing the transmitted position to a known position of the at least one cell; and determining that at least one cell of the array is inoperative if the transmitted position does not equal the know position.
Claim 2
Dependent Claim
318 words
In a parallel data processing system comprised of at least a two dimensional array of data processing cells, each of the cells comprising a plurality of input and output communication signal lines for electrically coupling to at least all immediately neighboring cells, at least one cell disposed at a unique position at an edge of the array having input communication signal lines coupled to a predetermined logic state, a method of determining by the control data processor that at least one of the cells of the array is inoperable, the method comprising the steps of: initially resetting the cells of the array to a common processing state; determining by each of the cells a position of the cell within the array, the step of determining a position including the steps of: initiating an input signal line logic state determination processing state within all of the cells of the array; detecting, by the at least one cell at the edge of the array, the predetermined logic state; determining from the detected predetermined logic state that the cell is located at the unique position within the array; communicating the position of the cell to at least one other neighboring cell whereby the cell so communicated to is enabled to determine its position within the array relative to the unique position of the cell disposed at the edge of the array, each of the cells within the array communicating its relative position to at least one neighboring cell until each of the cells within the array has determined its position relative to the unique position; the method further comprising the steps of: transmitting the position of at least one cell to the control data processor; comparing the transmitted position to a known position of the at least one cell; and determining that at least one cell of the array is inoperative if the transmitted position does not equal the know position.
Claim 3
Dependent Claim
48 words
A method as set forth in claim 1, wherein each of the cells comprises data processing means and wherein the step of initially resetting is accomplished by the control data processor simultaneously asserting an enabling logic state at a reset input of each of the data processing means.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |