Programmable configurable digital crossbar switch

Claim 2

A programmable reconfigurable digital crossbar switch, comprising: a plurality of multiplexer logic control ports; an m-bit internal data bus coupled to each of said multiplexer logic control ports for the interchange of data between any one of said multiplexer logic control ports and any other of said multiplexer control ports, whereby m is an integer greater than zero; a plurality of n-bit input/output data buses, each coupled to a respective one of said multiplexer logic control ports for the interchange of data between said multiplexer logic control ports and external devices, whereby n is an integer greater than zero; an n-bit port-to-port data transfer data bus sequentially interconnecting said plurality of multiplexer logic control ports in a looping configuration for the interchange of data between adjacent said multiplexer logic control ports; and control means operatively coupled to each of said multiplexer logic control ports for controlling a flow of data into and out of each of said multiplexer logic control ports and between each of said multiplexer logic control ports.

Claim 3

The digital crossbar switch of claim 1, wherein said control means comprises: an n-bit configuration control/memory unit for receiving data from one of said n-bit input/output data buses or from said n-bit port-to-port data transfer data bus and for controlling data transfer functions of said multiplexer logic control port when said port is in a normal operational mode.

Claim 4

The digital crossbar switch of claim 2, wherein said control means further comprises an m-bit to n-bit multiplexer operatively connected to said m-bit internal data bus ad controlled by said configuration control/memory unit to select data from any of said plurality of multiplexer logic control ports and output said data on said input/output data bus associated with said multiplexer logic control port.

Claim 5

The digital crossbar switch of claim 3, wherein said control means further comprises a control buffer connected in series with said input output data bus and controlled by said configuration control/memory unit to switch said input/output data bus between a mode for inputting data and a mode for outputting data.

Claim 6

The digital crossbar switch of claim 4, wherein said control means further comprises a configuration memory multiplexer having a first input coupled to the output of said control buffer, a second input coupled to said n-bit port-to-port data transfer data bus, and an output connected to said configuration control/memory unit, said multiplexer adapted to input data from said input/output data bus to said configuration control/memory unit in a first mode and to input data from a port adjacent said multiplexer logic control port to said configuration control/memory unit in a second mode.

Claim 7

The digital crossbar switch of claim 4, wherein said control means further comprises a first in first out data buffer operatively connected between said configuration control/memory unit and said internal data bus, and controlled by said configuration control/memory unit to receive data from said input/output data bus and to transfer said data to said internal data bus.

Claim 8

The digital crossbar switch of claim 4, wherein said control means further comprises a first in first out data buffer operatively controlled by said configuration control/memory unit; and a FIFO select multiplexer having a first input operatively connected to the output of said m-bit to n-bit multiplexer, and a second input operatively connected to said input/output data bus, and an output for providing input to said FIFO data buffer, said FIFO select multiplexer operating to select between said first and second inputs and to provide said selected input data to said FIFO data buffer, said FIFO data buffer operating under control of said configuration control/memory unit to provide said selected input data to said internal data bus.

Claim 9

The digital crossbar switch of claim 3, wherein said configuration control/memory unit is operatively connected to said n-bit port-to-port data transfer data bus for providing data directly from said configuration control/memory unit an adjacent multiplexer logic control port.

Claim 10

The digital crossbar switch of claim 1, wherein said control means further comprises bit reverse logic operatively connected to said internal data bus and operating under control of said configuration control/memory unit to swap bit locations of inputted data in a predetermined pattern and present said bit swapped data back to said internal data bus.

Claim 11

The digital crossbar switch of claim 1, wherein said control means further comprises data buffer means for inputting data from said n-bit input/output data bus, said m-bit internal data bus, or said n-bit port-to-port data transfer data bus at a first clock rate and outputting said data to said m-bit internal data bus at a second clock rate.

Claim 12

The digital crossbar of claim 10, wherein said first clock rate is faster than said second clock rate.

Claim 13

The digital crossbar switch of claim 2, further comprising a global control register for controlling the source of input data transferred into said configuration control/memory unit.

Claim 14

A digital crossbar switch, comprising: a plurality of memory control ports each having an external data port for receiving and transmitting data on an input/output data bus, an internal data input port for receiving data from a first adjacent one of said plurality of memory control ports, an internal data output port for transmitting data to a second adjacent one of said plurality of memory control ports, and an internal global data port for receiving data from and transmitting data to other said memory control ports; an internal port-to-port data transfer data bus sequentially interconnecting said plurality of memory control ports in a looping configuration for carrying data between adjacent said memory control ports, each of said internal data input ports being coupled to the internal data output port of an adjacent one of said memory control ports whereby no one of said internal data input ports is coupled to more than one of said internal data output ports, and no one of said internal data output ports is coupled to more than one of said internal data input ports; and an internal global data bus connecting each of said internal global data ports for carrying data between said memory control ports.

Claim 15

A digital crossbar switch, comprising: a plurality of memory control ports each having an external data port for receiving and transmitting data on an input/output data bus, an internal data input port for receiving data from a first adjacent one of said plurality of memory control ports, an internal data output port for transmitting data to a second adjacent one of said plurality of memory control ports, and an internal global data port for receiving data from and transmitting data to other said memory control ports; an internal port-to-port data transfer data bus sequentially interconnecting said plurality of memory control ports in a looping configuration for carrying data between adjacent said memory control ports, each of said internal data input ports being coupled to the internal data output port of an adjacent one of said memory control ports whereby no one of said internal data input ports is coupled to more than one of said internal data output ports, and no one of said internal data output ports is coupled to more than one of said internal data input ports; and an internal global data bus connecting each of said internal global data ports for carrying data between said memory control ports.