US5038282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Synchronous processor with simultaneous instruction processing and data transfer
Assignee: Massachusetts Institute of Technology
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Filing: 1988-05-11
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Granted: 1991-08-06
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Expires: 2008-05-11
Abstract
Abstract In a single instruction multiple data synchronous processor, each slave processor of an array includes a computational element and an isolated slave memory. Instructions broadcast to the slave processors may be processed simultaneously with data transfers between slave memories through communications registers and between the slave memories and an I/O processor through I/O registers. A multiplexer in each slave processor selects as an input to the communications register a signal from an adjacent slave or a nonadjacent slave to bypass a column in the array. Broadcast instructions may be overridden by individual slave processors by conditional instructions which set the otherwise unused program counter of the computational element. An array master, communication master and input/out processor may process respective sets of instructions in parallel, each addressing slave memories through a common memory controller. Code handled by the array master may be separated into control code processed by the array master and computation code broadcast to the slave processors by a translator. An incremental addressing scheme is provided. The translator may unroll one type of loop instruction to provide straight-line code processed by the slave processors or may retain loop instructions for processing as control code in the array master.
Inventors
- 👤 Ira H. Gilbert
- 👤 Nicodemo A. Ciccia
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3885; G06F15/00; G06F15/76; G06F15/80; G06F15/8007; G06F9/30003; G06F9/3005; G06F9/30065; G06F9/30072; G06F9/30076; G06F9/30087; G06F9/3836; G06F9/3842; G06F9/3877; G06F9/3879; G06F9/3887; G06F9/38873; G06F9/44; G06F9/455; G06F9/45504
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
243 words
A parallel data processing system comprising: an array of slave processors which simultaneously process respective data streams, each slave processor of the array comprising a multibit computational element having local memory, an external data memory which stores data to be transferred to and processed by the computational element, and a communications register for data being transferred between the external data memory and another slave processor of the array, each slave processor allowing for simultaneous processing of instructions by the computational element and transfer of data from the external data memory to the communications register; an array master processor which processes an operational set of instructions and broadcasts a single computational instruction stream to the slave processors of the array for parallel processing of data; a communication master processor which processes a communications set of instructions to control transfers of data from slave processors of the array to other slave processors of the array, the array master processor and the communication master processor processing the operational and communications sets of instructions in parallel; and a data memory controller responsive to simultaneous requests from the array master processor and the communications master processor for arbitrating said requests and initiating control signals for said communications register and external data memory to control addressing of the external data memory of each slave processor of the array in transfers within each slave processor between the external data memory and each of the computational element and the communications register.
Claim 2
Dependent Claim
243 words
A parallel data processing system comprising: an array of slave processors which simultaneously process respective data streams, each slave processor of the array comprising a multibit computational element having local memory, an external data memory which stores data to be transferred to and processed by the computational element, and a communications register for data being transferred between the external data memory and another slave processor of the array, each slave processor allowing for simultaneous processing of instructions by the computational element and transfer of data from the external data memory to the communications register; an array master processor which processes an operational set of instructions and broadcasts a single computational instruction stream to the slave processors of the array for parallel processing of data; a communication master processor which processes a communications set of instructions to control transfers of data from slave processors of the array to other slave processors of the array, the array master processor and the communication master processor processing the operational and communications sets of instructions in parallel; and a data memory controller responsive to simultaneous requests from the array master processor and the communications master processor for arbitrating said requests and initiating control signals for said communications register and external data memory to control addressing of the external data memory of each slave processor of the array in transfers within each slave processor between the external data memory and each of the computational element and the communications register.
Claim 3
Dependent Claim
68 words
A data processing system as claimed in claim 1 further comprising an input/output (I/O) processor which processes an I/O set of instructions to control transfer of data between slave processors of the array and a system memory, the I/O processor processing the I/O set of instructions in parallel with processing of the operational and communications sets of instructions by the array master processor and the communication master processor.
Claim 4
Dependent Claim
80 words
A data processing system as claimed in claim 2 wherein each slave processor further comprises an I/O register for data being transferred between the external data memory and the system memory and a communications register for data being transferred between the external data memory and another slave processor of the array, the I/O register and communications register allowing for simultaneous transfer of data between the slave processor and the system memory and between the slave processor and other slave processors.
Claim 5
Dependent Claim
80 words
A data processing system as claimed in claim 2 wherein the array master processor processes an operational set of instructions, the operational set of instructions including control code and computational code, the computational code being broadcast to the slave processors of the array for parallel processing of data and the control code being processed by the array master processor, blocks of control code and blocks of computational data being processed simultaneously by tha array master proccessor and the slave processors.
Claim 6
Dependent Claim
80 words
A data processing system as claimed in claim 1 wherein the array master processor processes an operational set of instructions, the operational set of instructions including control code and computational code, the computational code being broadcast through the slave processors of the array for parallel processing of data and the control code being processed by the array master processor, blocks of control code and blocks of computational data being processing simultaneously by the array master processor and the slave processors.
Claim 7
Dependent Claim
308 words
A parallel data processing system comprising: an array of slave processors which simultaneously process respective data streams, each slave processor of the array comprising a multibit computational element having local memory, an external data memory which stores data to be transferred to and processed by the computational element, an input/output (I/O) register for data being transferred between the slave memory and a system memory, and a communications register for data being transferred between the external data memory and another slave processor of the array, each slave processor allowing for simultaneous processing of instructions by the computational element and transfer of data from the external data memory to the I/O register and to the communications register; an array master processor which processes an operational set of instructions and broadcasts a single instruction stream to the slave processors of the array for parallel processing of data; a communication master processor which processes a communications set of instructions to control transfers of data between slave processors of the array; an I/O processor which processes an I/O set of instructions to control transfer of data between slave processors of the array and the system memory; and a data memory controller responsive to simultaneous requests from the array master processor, the communications master processor and the I/O processor for arbitrating said requests and initiating control signals for said communications register, said I/O register and said external data memory to control addressing of the external data memory of each slave processor of the array in transfers within each slave processor between the external data memory and each of the computational element, I/O register and communications register; the array master processor, the communications master processor and the I/O processor processing the computational, communications and I/O sets of instructions in parallel for simultaneous transfers of instructions and data to and from and between the slave processors.
Claim 8
Dependent Claim
308 words
A parallel data processing system comprising: an array of slave processors which simultaneously process respective data streams, each slave processor of the array comprising a multibit computational element having local memory, an external data memory which stores data to be transferred to and processed by the computational element, an input/output (I/O) register for data being transferred between the slave memory and a system memory, and a communications register for data being transferred between the external data memory and another slave processor of the array, each slave processor allowing for simultaneous processing of instructions by the computational element and transfer of data from the external data memory to the I/O register and to the communications register; an array master processor which processes an operational set of instructions and broadcasts a single instruction stream to the slave processors of the array for parallel processing of data; a communication master processor which processes a communications set of instructions to control transfers of data between slave processors of the array; an I/O processor which processes an I/O set of instructions to control transfer of data between slave processors of the array and the system memory; and a data memory controller responsive to simultaneous requests from the array master processor, the communications master processor and the I/O processor for arbitrating said requests and initiating control signals for said communications register, said I/O register and said external data memory to control addressing of the external data memory of each slave processor of the array in transfers within each slave processor between the external data memory and each of the computational element, I/O register and communications register; the array master processor, the communications master processor and the I/O processor processing the computational, communications and I/O sets of instructions in parallel for simultaneous transfers of instructions and data to and from and between the slave processors.
Claim 9
Dependent Claim
80 words
A data processing system as claimed in claim 6 wherein the array master processor processes an operational set of instructions, the operational set of instructions including control code and computational code, the computational code being broadcast through the slave processors of the array for parallel processing of data and the control code being processing by the array master processor, blocks of control code and blocks of computational data being processed simultaneously by the array master processor and the slave processors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-08-05 | 1995-02-04 | 1995-08-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-08-05 | 1999-02-04 | 1999-08-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-08-05 | 2003-02-04 | 2003-08-06 | $7700.00 | Window Closed / Lapsed |