Single instruction multiple data (SIMD) cellular array processing apparatus with on-board RAM and address generator apparatus

Claim 1

In a cellular array of a type employing a plurality of processors arranged in a matrix of rows and columns wherein each processor in said matrix can communicate with other processors to the left and right and up and down in horizontal and vertical directions of the matrix to perform arithmetic operations, an improvement therewith comprising: a plurality N of said processors each configured to operate on words J bits wide, said plurality of N processors being arranged in one row, wherein N is a positive integer greater than two; a corresponding plurality N of separate memory means, wherein each said separate memory means has an address input and a data output, and is associated with and coupled to a respective one of said plurality of N processors, and wherein each said separate memory means stores and outputs data words J bits wide through its data output to its associated processor in response to an address provided through its address input; address decoder means coupled to the address inputs of said plurality of N memory means, said address decoder means being operable to receive a global address provided thereto and to globally address said address inputs in parallel such that said memory means output data words in parallel to their associated processors; an external bus interface accommodating data words at least 2J bits wide, and an external memory coupled to said external bus interface having a number of addressable word locations larger than that of said memory means; a common bus accommodating data words at least 2J bits wide which is coupled to each of said plurality of N processors, to said external bus interface, and to said address decoder means for said plurality of N separate memory means; and a number P of at least two of said plurality of N processors being selected as an address generator for said one row of processors, said selected address-generating P processors each contributing data words J bits wide which are combined together to output a global address on said common bus P×J bits wide, and the other N-P processors of said plurality of N processors being selected to operate in parallel so as to process data output from said memory means of a combined width of (N-P)×J bits; wherein said P processors selected as said address generator to generate said global address on said common bus are used to address said memory means in parallel through said address decoder means and cause said memory means simultaneously to provide data of combined width of (N-P)×J bits to their associated (N-P) processors in said one row, as well as to address a larger capacity of external memory of up to 2 P ×J word locations through said address P×J bits wide provided on said common bus to said external bus interface.