Processor having a plurality of CPUS with one CPU being normally connected to common bus

Claim 2

A processor module comprising: a common bus for transferring first and second information; a first CPU providing an always active bus request signal so as to be normally connected to said common bus for processing the first information from said common bus to generate first data from the first information; a second CPU for processing the second information from said common bus to generate second data from the second information, for generating an access request signal requesting connection of said second CPU to said common bus, and for terminating the access request signal upon termination of the requirement of said second CPU for access to said common bus; first and second local buses connected respectively to said first and second CPUs, for transferring the first and second information, respectively; said first CPU being responsive to the access request signal from said second CPU for providing a disconnect acknowledge signal; and a controller for normally connecting the first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto.

Claim 3

A processor module according to claim 1, further comprising a memory for storing the first and second data from said first and second CPUs for application to said first and second CPUs respectively.

Claim 4

A processor module according to claim 2, wherein the second information is information for supporting the first information, said first CPU includes means for processing the first information representing a predetermined control algorithm for an object, and said second CPU includes means for performing backup processing to modify the control algorithm and data handled by said first CPU based on the first and second information, to supply an instruction to said first CPU and to manage the operation of said first CPU.

Claim 5

A processor module according to claim 2, wherein said memory further includes means for issuing an interrupt signal to said second CPU in response to an instruction from said first CPU to cause said second CPU to access said memory.

Claim 6

A processor module according to claim 2, wherein said memory further includes means for issuing an interrupt signal to said first CPU in response to an instruction from said second CPU to cause said first CPU to access said memory.

Claim 7

A processor system comprising: a plurality of processors, each processor including: (a) a common bus for transferring first and second information; (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information from said common bus to generate first data from the first information, and selectively generating a first system bus access request signal while processing the first information, (c) a second CPU for processing the second information from said common bus to generate second data from the second information, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating a second system bus access request signal while processing the second information, (d) a memory for storing the first and second data from said first and second CPUs for application to said first and second CPUs, (e) first and second local buses connected respectively to said first and second CPUs, for transferring the first and second information, respectively, (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto; a system bus connected to said plurality of processors; and a system switch for connecting said system bus to the common bus of a selected one of said plurality of processors in response to a system bus access request signal from said selected processor.

Claim 8

A processor system comprising: a plurality of processors, each processor including: (a) a common bus for transferring first and second information; (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information from said common bus to generate first data from the first information, and selectively generating a first system bus access request signal while processing the first information, (c) a second CPU for processing the second information from said common bus to generate second data from the second information, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating a second system bus access request signal while processing the second information, (d) a memory for storing the first and second data from said first and second CPUs for application to said first and second CPUs, (e) first and second local buses connected respectively to said first and second CPUs, for transferring the first and second information, respectively, (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto; a system bus connected to said plurality of processors; and a system switch for connecting said system bus to the common bus of a selected one of said plurality of processors in response to a system bus access request signal from said selected processor.

Claim 9

A processor system according to claim 6, wherein said first CPU includes means for processing the first information representing a predetermined control algorithm for an object, and said second CPU includes means for performing back-up processing to modify a control algorithm and data handled by said first CPU based on the first and second information, to supply an instruction to said first CPU and to manage the operation of said first CPU.

Claim 10

A processor system according to claim 6, wherein each said memory includes means for issuing an interrupt signal to the corresponding said second CPU in response to an instruction from the corresponding said first CPU to cause said corresponding said second CPU to access said memory.

Claim 11

A processor system according to claim 6, wherein each said memory includes means for issuing an interrupt signal to the corresponding said first CPU in response to an instruction from the corresponding said second CPU to cause said corresponding said first CPU to access said memory.

Claim 12

A processor system for controlling an object comprising: a plurality of processors, each processor including: (a) a common bus for transferring first and second information; (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information to control a portion of the object based on a control algorithm predetermined for the object, and selectively generating a first system bus access request signal and instructions while processing the first information, (c) a second CPU for processing the second information to supply instructions to said first CPU and to manage said first CPU to cause said second CPU to perform backup of said first CPU, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating another first system bus access request signal and instructions while processing the second information, (d) a memory for storing the first and second data respectively obtained from processing by said first and second CPUs in response to the instructions from said first and second CPUs, (e) first and second local buses connected to first and second CPUs, respectively, for transferring the first and second information, respectively, (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto; a system bus connected to said plurality of processors; and a first system switch responsive to a first system bus access request signal from one of said processors to connect said first system bus to the common bus of said one of said processors.

Claim 13

A processor system for controlling an object comprising: a plurality of processors, each processor including: (a) a common bus for transferring first and second information; (b) a first CPU providing an always active bus request signal so as to be normally connected to said common bus, for processing the first information to control a portion of the object based on a control algorithm predetermined for the object, and selectively generating a first system bus access request signal and instructions while processing the first information, (c) a second CPU for processing the second information to supply instructions to said first CPU and to manage said first CPU to cause said second CPU to perform backup of said first CPU, for generating a common bus access request signal upon requirement of said second CPU for access to said common bus, for terminating the common bus access request signal after termination of processing by said second CPU using said common bus, and for selectively generating another first system bus access request signal and instructions while processing the second information, (d) a memory for storing the first and second data respectively obtained from processing by said first and second CPUs in response to the instructions from said first and second CPUs, (e) first and second local buses connected to first and second CPUs, respectively, for transferring the first and second information, respectively, (f) said first CPU being responsive to the access request signal from the second CPU for providing a disconnect acknowledge signal, and (g) a controller for normally connecting said first CPU to said common bus and being responsive to the disconnect acknowledge signal for disconnecting said first CPU from said common bus, for connecting said second CPU to said common bus through said second local bus and for enabling access thereto, said controller being responsive to termination of the access request signal from said second CPU and the always active bus request signal from said first CPU for connecting said first CPU to said common bus through said first local bus and enabling access thereto; a system bus connected to said plurality of processors; and a first system switch responsive to a first system bus access request signal from one of said processors to connect said first system bus to the common bus of said one of said processors.

Claim 14

A processing system according to claim 10, wherein said second CPU includes means for selectively generating a second system bus access request signal while processing the second information, and said processing system further comprises: a second system bus connected to said plurality of processors; and a second system switch responsive to a second system bus access request signal from another one of said processors to connect said second system bus to said second local bus of said another one of said processors.

Claim 15

A processing system according to claim 10, wherein said second CPU includes means for performing backup processing to modify the control algorithm and data handled by said first CPU based on the second information.

Claim 16

A processing system according to claim 10, wherein each said memory includes means for issuing an interrupt signal to the corresponding said second CPU in response to one of the instructions from the corresponding said first CPU to cause said corresponding said second CPU to access said memory.

Claim 17

A processing system according to claim 10, wherein each said memory includes means for issuing an interrupt signal to the corresponding said first CPU in response to one of the instructions from the corresponding said second CPU to cause said corresponding said first CPU to access said memory.

Claim 18

A processing system according to claim 10, further comprising a system common memory shared by said plurality of processors and connected to said first system bus, for storing information necessary for controlling the object.

Claim 19

A processing system according to claim 10, further comprising system common I/O shared by said plurality of processors and connected to said first system bus, for supplying instructions to the object portions based on control information from said processors, respectively, for selectively processing information of the object, and for supplying the information onto said first system bus.

Claim 20

A processing system according to claim 11, further comprising a system common memory shared by said plurality of processors and connected to said second system bus, for storing information necessary for the backup of said first CPU.

Claim 21

A processing system according to claim 11, further comprising system common I/O shared by said plurality of processors and connected to said second system bus, for selectively processing state information of the object portions, and for supplying the state information onto said first system bus.