EP0123509A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Computer vector multiprocessing control
Assignee: Cray Research LLC
•
Filing: 1984-04-18
•
Granted: —
•
Expires: 2004-04-18
Abstract
Abstract A multiprocessing system and method for multiprocessing disclosed. A pair of processors (10,11) are provided, and each are connected to a central memory (12) through a plurality of memory reference ports. The processors are further each connected to the plurality of shared registers (50) which may be directly addressed by either processor at rates commensurate with intra-processor operation. The shared registers include registers for holding scalar and address information and registers for holding information to be used in coordinating the transfer of information through the shared registers. A multiport memory is provided and includes a conflict resolution circuit (290) which senses and prioritizes conflicting references to the central memory between CPU (20). Each CPU is interfaced with the central memory through three ports, with each of the ports handling different ones of several different types of memory references which may be made. At least one t/0 port is provided to be shared by the processors in transferring information between the central memory and peripheral storage devices. A vector register design is also disclosed for use in vector processing computers, and provides for at least two independently addressable memories for vector data for delivery to or acceptance from a functional unit. The method of multiprocessing permits multitasking in the multiprocessor, in which the shared registers allow independent tasks of different jobs or related tasks of a single job to be run concurrently, and facilitates multithreading of the operating system by permitting multiple critical code regions to be independently synchronized.
Inventors
- 👤 Steve S. Chen
- 👤 Alan J. Schiffleger
- 👤 Eugene R. Somdahl
- 👤 Lee Higbie
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-25 21:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F15/00; G06F15/16; G06F15/163; G06F15/17; G06F15/76; G06F15/80; G06F15/8053; G06F15/8092; G06F9/30076; G06F9/30087; G06F9/38; G06F9/3877; G06F9/3879
Claims Analysis
Total Claims: 26
Claim 1
Independent Claim
106 words
1 . A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; and, one or more shared registers and means for connecting said registers to said internal information paths of each of said processing machines so that said shared registers may be accessed at rates commensurate with intraprocessor operation.
Claim 2
Dependent Claim
106 words
1 . A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; and, one or more shared registers and means for connecting said registers to said internal information paths of each of said processing machines so that said shared registers may be accessed at rates commensurate with intraprocessor operation.
Claim 3
Dependent Claim
341 words
A multiprocessor vector processing system comprising: a central memory having a plurality of access paths; a plurality of vector processing machines each having internal data paths and each of said processing machines connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal data paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; one or more shared registers and means for connecting said registers to said internal paths of each of said processing machines so that said shared registers may be accessed at rates commensurate with intraprocessor operation; each of said vector processing machines including: a plurality of vector registers each for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, and functional unit including segmented means for holding data for operations not yet completed while receiving operands of successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector.
Claim 4
Dependent Claim
341 words
A multiprocessor vector processing system comprising: a central memory having a plurality of access paths; a plurality of vector processing machines each having internal data paths and each of said processing machines connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal data paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; one or more shared registers and means for connecting said registers to said internal paths of each of said processing machines so that said shared registers may be accessed at rates commensurate with intraprocessor operation; each of said vector processing machines including: a plurality of vector registers each for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, and functional unit including segmented means for holding data for operations not yet completed while receiving operands of successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector.
Claim 5
Independent Claim
234 words
A method of inter-processor communication in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, said method of direct communication comprising the steps of: a) providing a plurality of semaphore registers which may be addressed directly by any one of said processors through said internal paths; b) providing a plurality of information registers which may be addressed directly by any one of said processors through said internal paths; c) organizing said semaphore registers and said information registers into a plurality of clusters; d) providing a cluster code register for each processor to hold a code indicative of which, if any, of said clusters the processor may access; e) controlling access by the processors to said clusters with the operating system of said multiprocessor system, the operating system controlling access by altering the codes retained in said cluster code registers; and f) controlling access by the processors to the individual ones of said information registers with the semaphore registers, the semaphore registers associated with a cluster capable of holding code indicative of the status of the information registers or the status of software conditions in a processor.
Claim 6
Independent Claim
234 words
A method of inter-processor communication in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, said method of direct communication comprising the steps of: a) providing a plurality of semaphore registers which may be addressed directly by any one of said processors through said internal paths; b) providing a plurality of information registers which may be addressed directly by any one of said processors through said internal paths; c) organizing said semaphore registers and said information registers into a plurality of clusters; d) providing a cluster code register for each processor to hold a code indicative of which, if any, of said clusters the processor may access; e) controlling access by the processors to said clusters with the operating system of said multiprocessor system, the operating system controlling access by altering the codes retained in said cluster code registers; and f) controlling access by the processors to the individual ones of said information registers with the semaphore registers, the semaphore registers associated with a cluster capable of holding code indicative of the status of the information registers or the status of software conditions in a processor.
Claim 7
Independent Claim
178 words
A method of controlling inter-processor communication in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly by any one of the processors through said internal paths at rates commensurate with intra-processor operation, said method comprising the steps of: a) organizing said information registers into a plurality of clusters; b) designating certain ones of said information registers to hold information indicative of the operational status of software tasks being executed by the processors; c) restricting access to each of said clusters to certain ones of said processors; and d) coordinating the transfer of information between different processors permitted to access the same cluster by testing, setting and clearing the status information maintained in said certain ones of the information registers.
Claim 8
Independent Claim
178 words
A method of controlling inter-processor communication in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly by any one of the processors through said internal paths at rates commensurate with intra-processor operation, said method comprising the steps of: a) organizing said information registers into a plurality of clusters; b) designating certain ones of said information registers to hold information indicative of the operational status of software tasks being executed by the processors; c) restricting access to each of said clusters to certain ones of said processors; and d) coordinating the transfer of information between different processors permitted to access the same cluster by testing, setting and clearing the status information maintained in said certain ones of the information registers.
Claim 9
Independent Claim
202 words
A method of multitasking a software job between a plurality of processors in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly through said internal paths at rates commensurate with intra-processor operation, said information registers organized into a plurality of clusters, the-access to any cluster by a processor being programmable, said method comprising the steps of: a) providing an operating system stored in said central memory; b) calling said operating system into one of said processors for execution; c) analyzing the processor requirements of said job with said operating system; d) assigning one or more tasks associated with said job to one or more of said processors through said operating system; e) programming access to said clusters by said processors through said operating system; f) causing said task or tasks to be executed by said processors; and g) repeating steps b) through f).
Claim 10
Independent Claim
202 words
A method of multitasking a software job between a plurality of processors in a multiprocessor data processing system including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly through said internal paths at rates commensurate with intra-processor operation, said information registers organized into a plurality of clusters, the-access to any cluster by a processor being programmable, said method comprising the steps of: a) providing an operating system stored in said central memory; b) calling said operating system into one of said processors for execution; c) analyzing the processor requirements of said job with said operating system; d) assigning one or more tasks associated with said job to one or more of said processors through said operating system; e) programming access to said clusters by said processors through said operating system; f) causing said task or tasks to be executed by said processors; and g) repeating steps b) through f).
Claim 11
Independent Claim
284 words
A method of multiprocessing in a vector processing system including two or more processors each having a plurality of vector registers for handling ordered arrays of data for processing through functional units and including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly by any one of the processors through said internal paths at rates commensurate with intra- processor operation, said method comprising the steps of: a) storing ordered arrays of vector data to be processed in said central memory; b) storing scalar and address information associated with a job to be executed in said central memory; c) causing one of said processors to retrieve said scalar and address information and to retrieve vector data to be processed which is associated with said address information; d) processing said vector data through said one processor to produce a result vector of data or result scalar data; e) storing said result vector of data in said central memory in certain memory locations; f) storing said result scalar data and new address information indicative of the location of said result vector of data in said central memory in said information registers; and g) causing a different one of said processors to retrieve said result scalar data and new address information from said information registers to permit said different processor to retrieve said result vector of data from the central memory and perform further processing.
Claim 12
Independent Claim
284 words
A method of multiprocessing in a vector processing system including two or more processors each having a plurality of vector registers for handling ordered arrays of data for processing through functional units and including a central memory shared between the processors in which each processor includes internal paths for control and data information and in which each processor communicates with said central memory through one or more ports which receive reference requests from said internal paths and generate and control references to the central memory, and a plurality of information registers which may be addressed directly by any one of the processors through said internal paths at rates commensurate with intra- processor operation, said method comprising the steps of: a) storing ordered arrays of vector data to be processed in said central memory; b) storing scalar and address information associated with a job to be executed in said central memory; c) causing one of said processors to retrieve said scalar and address information and to retrieve vector data to be processed which is associated with said address information; d) processing said vector data through said one processor to produce a result vector of data or result scalar data; e) storing said result vector of data in said central memory in certain memory locations; f) storing said result scalar data and new address information indicative of the location of said result vector of data in said central memory in said information registers; and g) causing a different one of said processors to retrieve said result scalar data and new address information from said information registers to permit said different processor to retrieve said result vector of data from the central memory and perform further processing.
Claim 13
Dependent Claim
148 words
A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; a plurality of shared information registers for storing scalar and address information, each of said registers connected to said internal information paths of said processors for direct addressing by said processors; and a plurality of semaphore registers each capable of being set, cleared or tested through software instructions by any one of said processors and each associated with a certain one of said information registers to provide software means for coordinating the transfer of information between jobs executed in said processors.
Claim 14
Dependent Claim
148 words
A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; a plurality of shared information registers for storing scalar and address information, each of said registers connected to said internal information paths of said processors for direct addressing by said processors; and a plurality of semaphore registers each capable of being set, cleared or tested through software instructions by any one of said processors and each associated with a certain one of said information registers to provide software means for coordinating the transfer of information between jobs executed in said processors.
Claim 15
Dependent Claim
290 words
A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; a plurality of clusters of shared information registers, each of said information registers connected to permit direct addressing by any one of said processors through said internal information paths; a plurality of clusters of semaphore registers each associated with a corresponding one of said clusters of information registers, each of said semaphore registers connected to permit any one of said processors to test and set or clear the contents thereof-directly through said internal information paths; each of said processors having associated therewith access control means which may be programmed to direct a processor attempting to access said information or semaphore registers to a certain one of said clusters or to prevent a processor from access to any one of said clusters; each of said processors also having associated therewith an instruction issue control means for preventing a processor from issuing a semaphore register test and set instruction when the register to be set is already set and to hold the issuance of the set instruction until the register is cleared; and deadlock interrupt means for monitoring the holding of test and set instructions by the processors and for interrupting at least one of said processors when there is no possibility that a particular one of said processors will be permitted to issue the test and set instruction which it is waiting to issue.
Claim 16
Dependent Claim
290 words
A multiprocessor system comprising: a central memory having a plurality of access paths; a plurality of processing machines each having internal information paths and each connected to said central memory access paths through a plurality of ports, said ports for receiving reference requests over said internal information paths from said processing machines and for generating and controlling memory references to said central memory through said access paths; a plurality of clusters of shared information registers, each of said information registers connected to permit direct addressing by any one of said processors through said internal information paths; a plurality of clusters of semaphore registers each associated with a corresponding one of said clusters of information registers, each of said semaphore registers connected to permit any one of said processors to test and set or clear the contents thereof-directly through said internal information paths; each of said processors having associated therewith access control means which may be programmed to direct a processor attempting to access said information or semaphore registers to a certain one of said clusters or to prevent a processor from access to any one of said clusters; each of said processors also having associated therewith an instruction issue control means for preventing a processor from issuing a semaphore register test and set instruction when the register to be set is already set and to hold the issuance of the set instruction until the register is cleared; and deadlock interrupt means for monitoring the holding of test and set instructions by the processors and for interrupting at least one of said processors when there is no possibility that a particular one of said processors will be permitted to issue the test and set instruction which it is waiting to issue.
Claim 17
Dependent Claim
246 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; - . at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; paths select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, as results from the functional unit become available.
Claim 18
Dependent Claim
246 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; - . at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; paths select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector, as results from the functional unit become available.
Claim 19
Dependent Claim
296 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements -of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector as results from the functional unit become available, said control means further operative to resolve reference conflicts between simultaneously attempted read and write operations to the same memory bank and to cause one of said attempted references to be forced to another memory bank so that subsequent simultaneous read and write operations occur in different ones of said memory banks.
Claim 20
Dependent Claim
296 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including a plurality of individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and, control means associated with said vector registers and responsive to program instructions, said control means being operative in conjunction with a vector register selected as an operand register in a vector processing operation to successively transmit the elements -of the ordered set of data from the vector register to a functional unit as the functional unit and the elements become available, said control means being operative in conjunction with a vector register selected as a result register in a vector processing operation to receive and store successive results transmitted from a functional unit as elements of an ordered set of data representing a result vector as results from the functional unit become available, said control means further operative to resolve reference conflicts between simultaneously attempted read and write operations to the same memory bank and to cause one of said attempted references to be forced to another memory bank so that subsequent simultaneous read and write operations occur in different ones of said memory banks.
Claim 21
Dependent Claim
281 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including at least two individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and control means associated with each of said vector registers and responsive to program instructions, said control means including a vector read control and a vector write control, said vector read control including means for monitoring the availability of operands and producing a data ready signal indicative thereof that may be monitored by another vector read controls to determine when both are ready to send an operand to a functional unit, said read control further producing a go write signal each time an. operand is sent to a functional unit, said go write signal being sent to the functional along with the operand and delayed in the functional unit until the corresponding result is produced thereby and then delivered to the vector write control associated with the vector register designated to receive the result to signal said register that a result is to be accepted for writing to a memory bank.
Claim 22
Dependent Claim
281 words
Vector processing apparatus for a computer having a main memory, comprising: a plurality of vector registers each including at least two individually addressable memory banks for holding a plurality of elements of an ordered set of data; at least one arithmetic or logical functional unit having an input for receiving operands and an output for delivering results, said functional unit including segmented means for holding data for operations not yet completed while receiving operands for successive operations; path select means associated with said vector registers and responsive to program instructions for selectively connecting individual vector registers for transmission of data to or from said central memory, and for selectively connecting individual vector registers for transmitting data as operands to a functional unit and for receiving results from a functional unit; and control means associated with each of said vector registers and responsive to program instructions, said control means including a vector read control and a vector write control, said vector read control including means for monitoring the availability of operands and producing a data ready signal indicative thereof that may be monitored by another vector read controls to determine when both are ready to send an operand to a functional unit, said read control further producing a go write signal each time an. operand is sent to a functional unit, said go write signal being sent to the functional along with the operand and delayed in the functional unit until the corresponding result is produced thereby and then delivered to the vector write control associated with the vector register designated to receive the result to signal said register that a result is to be accepted for writing to a memory bank.
Claim 23
Dependent Claim
152 words
A multiprocessor system comprising: a central memory having a plurality of access paths, said central memory being subdivided into a plurality of independent banks each of which may be independently referenced concurrently, said access paths being connected to a plurality of said banks; a plurality of processing machines each connected to said central memory access paths through a plurality of ports, said ports for receiving central memory reference requests from said processing machines and for generating and controlling memory references to said central memory through said access paths; and memory reference conflict resolution means connected to each of said port means for coordinating and prioritizing conflicting memory reference requests to said central memory, said conflict resolution means being responsive to conflicting memory reference requests from said ports to one of said banks for causing one of said conflicting ports to delay execution of its reference request until the conflict has been resolved.
Claim 24
Dependent Claim
152 words
A multiprocessor system comprising: a central memory having a plurality of access paths, said central memory being subdivided into a plurality of independent banks each of which may be independently referenced concurrently, said access paths being connected to a plurality of said banks; a plurality of processing machines each connected to said central memory access paths through a plurality of ports, said ports for receiving central memory reference requests from said processing machines and for generating and controlling memory references to said central memory through said access paths; and memory reference conflict resolution means connected to each of said port means for coordinating and prioritizing conflicting memory reference requests to said central memory, said conflict resolution means being responsive to conflicting memory reference requests from said ports to one of said banks for causing one of said conflicting ports to delay execution of its reference request until the conflict has been resolved.
Claim 25
Independent Claim
163 words
A system for interfacing a main memory and vector registers for use in a vector processing computer, said system comprising: a main memory having a plurality of access paths and configured to permit concurrent read and write references thereto; a plurality of vector registers for holding a plurality of elements of an ordered set of data; each of said vector registers being connected to said main memory access paths through a plurality of ports, certain of said ports being dedicated to and controlled for reading data from said main memory and writing that data into a vector register, and the other of said ports being dedicated to and controlled for reading data from a vector register and writing that data into said main memory so that operand data may be transferred to said vector registers from the main memory while result data is transferred back to the main memory to permit a continuous flow of data between said registers and said main memory.
Claim 26
Independent Claim
163 words
A system for interfacing a main memory and vector registers for use in a vector processing computer, said system comprising: a main memory having a plurality of access paths and configured to permit concurrent read and write references thereto; a plurality of vector registers for holding a plurality of elements of an ordered set of data; each of said vector registers being connected to said main memory access paths through a plurality of ports, certain of said ports being dedicated to and controlled for reading data from said main memory and writing that data into a vector register, and the other of said ports being dedicated to and controlled for reading data from a vector register and writing that data into said main memory so that operand data may be transferred to said vector registers from the main memory while result data is transferred back to the main memory to permit a continuous flow of data between said registers and said main memory.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.