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US4495569A
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US
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Interrupt control for multiprocessor system with storage data controlling processor interrupted by devices
Assignee: Mitsubishi Electric Corp
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Filing: 1982-06-25
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Granted: 1985-01-22
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Expires: 2002-06-25
Abstract
Abstract A multiprocessor system includes a random access memory (85) for storing a processor number data specifying that an interrupt from any of a plurality of devices (6l to 6m) to any one of a plurality of processors (1l to 1n) is permitted. If and when an interrupt request signal is applied from the device (61) to an interrupt controller (8), a processor number data indicating a processor which the device (61) can interrupt is read out from the random access memory (85). The interrupt controller (8) applies an interrupt signal to a processor (11), for example, according to the processor number data. Correspondingly, the processor (11) applies a bus request signal to a bus controller (7). According to the bus request signal, the bus controller (7) controls a bus selecting circuit (3) to connect a local bus (21) of the processor (11) to a common bus (5).
Inventors
- 👤 Eiichi Kagawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:39
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/24; G06F13/38; G06F13/40; G06F13/4004; G06F13/4022
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
173 words
A multiprocessor system comprising: a plurality of processor means for generating a bus request signal, local buses individually connected to each of said processor means, a plurality of device means for generating an interrupt request signal, respectively, said device means being commonly controlled by each of said processor means, a common bus commonly connected to each of said device means, data storing means for storing destination data for specifying at least one of said plurality of processor means which is requested to be interrupted by each of said device means, interrupt controlling means responsive to the interrupt request signal from said device means for reading out the destination data from said data storing means for recognizing the processor means corresponding to the destination according to said destination data for providing an interrupt signal to the corresponding processor means, and bus selecting means for connecting a local bus of the corresponding processor means to said common bus according to the bus request signal from the processor mean to which said interrupt signal is provided.
Claim 2
Dependent Claim
173 words
A multiprocessor system comprising: a plurality of processor means for generating a bus request signal, local buses individually connected to each of said processor means, a plurality of device means for generating an interrupt request signal, respectively, said device means being commonly controlled by each of said processor means, a common bus commonly connected to each of said device means, data storing means for storing destination data for specifying at least one of said plurality of processor means which is requested to be interrupted by each of said device means, interrupt controlling means responsive to the interrupt request signal from said device means for reading out the destination data from said data storing means for recognizing the processor means corresponding to the destination according to said destination data for providing an interrupt signal to the corresponding processor means, and bus selecting means for connecting a local bus of the corresponding processor means to said common bus according to the bus request signal from the processor mean to which said interrupt signal is provided.
Claim 3
Dependent Claim
88 words
A multiprocessor system in accordance with claim 1, wherein identifying numbers are previously assigned to the respective device means, the respective identifying numbers being different from each other, said respective device means includes means for outputting as an interrupt request signal a signal based on said identifying number, said data storing means includes storage areas corresponding to the respective identifying numbers of said device means, and which further comprises means for applying destination data of said device means corresponding to said identifying number to the storage areas, respectively.
Claim 4
Dependent Claim
58 words
A multiprocessor system in accordance with claim 1, wherein said interrupt controlling means includes interrupt permitting signal generating means for applying interrupt permitting signals to said device means, and said respective device means includes interrupt request signal generating means responsive to said interrupt permitting signal from said interrupt permitting signal generating means for outputting an interrupt request signal.
Claim 5
Dependent Claim
65 words
A multiprocessor system in accordance with claim 3, wherein said interrupt controlling means includes interrupt instruction signal generating means for generating an interrupt instruction signal, and means for applying an interrupt signal to the processor means corresponding to the destination data based on the destination data read out from said data storing means and the interrupt instruction signal from said interrupt instruction signal generating means.
Claim 6
Dependent Claim
44 words
A multiprocessor system in accordance with claim 4, which further comprises means for enabling an interrupt instruction signal to be generated from said interrupt instruction signal generating means responsive to recognition of presence and/or absence of the destination data from said data storing means.
Claim 7
Dependent Claim
64 words
A multiprocessor system in accordance with claim 1, wherein said bus selecting means includes bus selecting signal generating means for generating a bus selecting signal based on the bus request signals from said processor means, and means responsive to the bus selecting signals from said bus selecting signal generating means for connecting the local bus of the corresponding processor means to the common bus.
Claim 8
Dependent Claim
209 words
A multiprocess system comprising: a plurality of processor means each including means for generating a unique bus request signal, local buses individually connected to each of said processor means, a plurality of device means each including means for generating a unique interrupt request signal, respectively, a common bus connected to each of said device means, said device means being commonly controlled by each of said processor means via said common bus, destination determining means for storing destination data for specifying at least one of said plurality of processor means to be interrupted by each of said device means, interrupt controlling means connected to said common bus means and to each of said processor means, said interrupt controlling means responsive to the interrupt request signal from said device means for reading out destination data from said destination determining means for identifying the processor means corresponding to said destination data and for providing an interrupt signal to the corresponding processor means, and bus selecting means connected to said local buses and to said common bus for connecting a local bus of the identified processor means corresponding to said destination data to said common bus according to the bus request signal from the processor means to which said interrupt signal is provided.
Claim 9
Dependent Claim
209 words
A multiprocess system comprising: a plurality of processor means each including means for generating a unique bus request signal, local buses individually connected to each of said processor means, a plurality of device means each including means for generating a unique interrupt request signal, respectively, a common bus connected to each of said device means, said device means being commonly controlled by each of said processor means via said common bus, destination determining means for storing destination data for specifying at least one of said plurality of processor means to be interrupted by each of said device means, interrupt controlling means connected to said common bus means and to each of said processor means, said interrupt controlling means responsive to the interrupt request signal from said device means for reading out destination data from said destination determining means for identifying the processor means corresponding to said destination data and for providing an interrupt signal to the corresponding processor means, and bus selecting means connected to said local buses and to said common bus for connecting a local bus of the identified processor means corresponding to said destination data to said common bus according to the bus request signal from the processor means to which said interrupt signal is provided.
References Cited (Backward Citations)
US4396978A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1988-01-22 | 1988-07-23 | 1989-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1992-01-22 | 1992-07-23 | 1993-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1996-01-22 | 1996-07-23 | 1997-01-22 | $7700.00 | Window Closed / Lapsed |