Single instruction multiple data (SIMD) cellular array processing apparatus employing a common bus where a first number of bits manifest a first bus portion and a second number of bits manifest a second bus portion

Abstract

Abstract In a cellular array including a matrixed array of processing elements, the processing elements are controlled by software to overcome manufacturing defects, to cooperate together to form words of varying size and to replace cells that become defective during the lifetime of the processor. These cells communicate with memory external to the chip via a time division multiplex bus. The bus is 32-bits wide and each cell is connected to both the upper half and the lower half of the bus. Configuration bits that are loaded into a cell cause communication over the top half or the bottom half of the bus according to the significance of the bits placed in the cells. Words between 16-bits and 246-bits in length may be formed in a case where 20 such cells are implemented on a single chip with four of the cells being deemed to be spare parts. For simplicity, typical word sizes would be 2n×16 bits although in principle any multiple of 16-bits may be obtained. Each cell contains a 16-bit multiport RAM providing general purpose registers for use by the programmer as well as systems registers. The systems registers accommodate the processor status word, a multiplier quotient register, a full-function arithmetic logic unit and path logic to connect the cells together and control the flow of information through the path logic according to the instruction being executed.

Inventors

• 👤 Steven G. Morton

Bibliographic Details