Single chip integrated circuit computer architecture

Claim 2

A computer system comprising: a single chip stored program digital computer implemented on a single integrated circuit chip, said single chip stored program digital computer including (1) an integrated circuit read only memory storing computer instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; (2) an integrated circuit alterable memory storing computer operands, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; and (3) an integrated circuit processing circuit coupled to the integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing circuit is implemented on said single integrated circuit chip.

Claim 3

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is arranged to store at least one of the computer instructions as an eight bit byte computer instruction, wherein said integrated circuit alterable memory is arranged to store at least one of the computer operands as a sixteen bit computer operand, and wherein said integrated circuit processing circuit is arranged to process a sixteen bit computer operand stored by said integrated circuit alterable memory in response to an eight bit byte computer instruction stored by said integrated circuit read only memory.

Claim 4

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is arranged to store the computer instructions as eight bit bytes.

Claim 5

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is arranged to store the computer instructions as eight bit bytes, wherein said integrated circuit processing circuit includes a transfer instruction execution circuit executing a transfer instruction, wherein said transfer instruction execution circuit includes a first accessing circuit accessing three sequential eight bit bytes stored by said integrated circuit read only memory and a transfer control circuit coupled to the first accessing circuit and transferring control to a next instruction in response to the three eight bit bytes accessed by said first accessing circuit.

Claim 6

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is arranged to store computer instructions as eight bit bytes, said computer system further comprising an integrated circuit transfer execution circuit coupled to the integrated circuit read only memory and executing a transfer instruction stored thereby, wherein said integrated circuit transfer execution circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit transfer circuit includes (a) a first accessing circuit accessing a first eight bit byte stored by said integrated circuit read only memory, (b) a first transfer circuit coupled to the first accessing circuit and generating a transfer signal in response to detecting of a particular code of said first eight bit byte, (c) a second accessing circuit coupled to the first transfer circuit and accessing a second eight bit byte and a third eight bit byte stored by said integrated circuit read only memory in response to the detecting of the particular code of said first eight bit byte by said first transfer circuit, (d) a second transfer circuit coupled to the second accessing circuit and generating a transfer address in response to the second eight bit byte and the third eight bit byte accessed by said second accessing circuit, and (e) a third accessing circuit coupled to the second transfer circuit and accessing a next instruction eight bit byte stored by said integrated circuit read only memory in response to the transfer address generated by said second transfer circuit.

Claim 7

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is a computer main program memory.

Claim 8

A computer system as set forth in claim 1, further comprising an integrated circuit micro-instruction circuit executing a plurality of micro-instructions under control of an instruction stored in said integrated circuit read only memory, wherein said integrated circuit micro-instruction circuit is implemented on said single integrated circuit chip.

Claim 9

A computer system as set forth in claim 1, further comprising an integrated circuit micro-operation circuit executing a plurality of sequential micro-operations under control of an instruction stored in said integrated circuit read only memory, wherein said integrated circuit micro-operation circuit is implemented on said single integrated circuit chip, and wherein said micro-operation circuit includes a micro-instruction circuit executing at least one micro-instruction for each of the plurality of sequential micro-operations.

Claim 10

A computer system as set forth in claim 1, further comprising: an integrated circuit address register storing a sixteen bit instruction address, wherein said integrated circuit address register is implemented on said single integrated circuit chip, and an integrated circuit instruction access circuit accessing an instruction stored by said integrated circuit read only memory in response to the sixteen bit instruction address stored by said integrated circuit address register, wherein said integrated circuit instruction access circuit is implemented on said single integrated circuit chip.

Claim 11

A computer system as set forth in claim 1, further comprising: an integrated cicuit interrupt circuit generating an interrupt signal, wherein said integrated circuit interrupt circuit is implemented on said single integrated circuit chip; an integrated circuit transfer circuit coupled to the integrated circuit interrupt circuit and accessing an interrupt instruction stored by said integrated circuit read only memory in response to the interrupt signal, wherein said integrated circuit transfer circuit is implemented on said single integrated circuit chip; and an integrated circuit return circuit coupled to the integrated circuit interrupt circuit and storing a return address in said integrated circuit alterable memory in response to the interrupt signal generated by said integrated circuit interrupt circuit, wherein said integrated circuit return circuit is implemented on said single integrated circuit chip.

Claim 12

A computer system as set forth in claim 1, wherein said integrated circuit processing circuit includes an integrated circuit accumulator register storing a computer operand, wherein said integrated circuit accumulator register is implemented on said single integrated circuit chip; an integrated circuit add circuit adding a computer operand stored by said integrated circuit accumulator register and a computer operand stored by said integrated circuit alterable memory in response to an add instruction stored by said integrated circuit read only memory, wherein said integrated circuit add circuit is implemented on said single integrated circuit chip; an integrated circuit subtract circuit subtracting a computer operand stored by said integrated circuit accumulator register and a computer operand stored by said integrated circuit alterable memory in response to a subtract instruction stored by said integrated circuit read only memory, wherein said integrated circuit subtract circuit is implemented on said single integrated circuit chip; an integrated circuit logical circuit logically processing a computer operand stored by said integrated circuit accumulator register and a computer operand stored by said integrated circuit alterable memory in response to a logical instruction stored by said integrated circuit read only memory, wherein said integrated circuit logical circuit is implemented on said single integrated circuit chip; and an integrated circuit transfer circuit generating a transfer signal in response to a transfer instruction stored by said integrated circuit read only memory, wherein said integrated circuit transfer circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit transfer circuit includes an accessing circuit accessing an instruction stored by said integrated circuit read only memory in response to the transfer signal generated by said integrated circuit transfer circuit and includes a return address storing circuit storing a return address in said integrated circuit alterable memory in response to the transfer signal generated by said integrated circuit transfer circuit.

Claim 13

A computer system as set forth in claim 1, wherein said integrated circuit processing circuit includes an inline circuit processing an inline instruction, said inline circuit including: a first accessing circuit accessing an inline instruction byte stored by said integrated circuit read only memory; a first inline execution circuit generating an inline signal in response to an inline instruction byte accessed by said first accessing circuit; a second accessing circuit coupled to said first inline execution circuit and accessing at least one inline computer operand byte stored by said integrated circuit read only memory in response to the inline signal; and a second inline execution circuit coupled to said second accessing circuit and processing the at least one inline computer operand byte accessed by said second accessing circuit.

Claim 14

A computer system as set forth in claim 1, wherein said integrated circuit read only memory is adapted to store at least one operand, wherein said integrated circuit processing circuit includes a loading circuit loading an operand stored by said integrated circuit read only memory into said integrated circuit alterable memory, and wherein said loading circuit includes: a first accessing circuit accessing a load instruction stored by said integrated circuit read only memory; a second accessing circuit accessing an operand to be loaded that is stored by said integrated circuit read only memory in response to the load instruction accessed by said first accessing circuit; and a storing circuit coupled to said first accessing circuit and to said second accessing circuit and storing the operand accessed by said second accessing circuit into said integrated circuit alterable memory in response to the load instruction accessed by said first accessing circuit.

Claim 15

A computer system as set forth in claim 1, further comprising an integrated circuit indirect transfer circuit providing indirect transfer of program control, wherein said integrated circuit indirect transfer circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit indirect transfer circuit includes: a first accessing circuit coupled to said integrated circuit read only memory and accessing an indirect transfer instruction stored by said integrated circuit read only memory; an indirect transfer execution circuit coupled to said first accessing circuit and generating an indirect transfer signal in response to an indirect transfer instruction accessed by said first accessing circuit; a second accessing circuit coupled to said integrated circuit alterable memory and to said indirect transfer execution circuit and accessing an indirect transfer address stored by said integrated circuit alterable memory in response to the indirect transfer signal; and a third accessing circuit coupled to said integrated circuit read only memory and to said second accessing circuit and accessing an instruction stored by said integrated circuit read only memory in response to the indirect transfer address accessed by said second accessing circuit.

Claim 16

A computer system as set forth in claim 1, further comprising a communication device communicating with an operator in response to the instructions stored by said integrated circuit read only memory.

Claim 17

A computer system as set forth in claim 1, further comprising an integrated circuit serial output circuit coupled to said integrated circuit read only memory and generating a serial output computer operand in response to at least one of the computer instructions stored by said integrated circuit read only memory, wherein said serial output circuit is implemented on said single integrated circuit chip.

Claim 18

A computer system as set forth in claim 1, further comprising an integrated circuit serial input circuit inputting a serial input computer operand in response to at least one of the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit serial input circuit is implemented on said single integrated circuit chip, and an integrated circuit alterable memory input circuit coupled to said integrated circuit alterable memory and to said integrated circuit serial input circuit and storing the serial input computer operand into said integrated circuit alterable memory in response to at least one of the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit alterable memory input circuit is implemented on said single integrated circuit chip.

Claim 19

A computer system as set forth in claim 1, wherein said computer system is a factored computer system; said factored computer system further comprising: a controller controlling a machine tool in response to a serial machine control signal generated by said single chip stored program digital computer; a display device displaying information to an operator in response to a serial display signal generated by said single chip stored program digital computer; a serial elemental extremity operating under computer coaction in response to a serial interface signal generated by said single chip stored program digital computer; a remote computer communicating with said single chip stored program digital computer in response to a serial communication signal; a parallel elemental extremity operating under computer coaction in response to a parallel interface signal generated by said single chip stored program digital computer; a physically distributed interface operating in response to a distributed interface signal generated by said single chip stored program digital computer; and wherein said single chip stored program digital computer further includes (a) an integrated circuit serial output circuit generating the serial machine control signal, the serial display signal, and the serial interface signal in response to at least one of the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit serial output circuit is implemented on said single integrated circuit chip, (b) an integrated circuit parallel output circuit generating the parallel interface signal in response to at least one of the computer instructions stored by said integrated circuit read only memory, (c) an integrated circuit serial communication circuit serially communicating with said remote computer with the serial communication signal, wherein said integrated circuit parallel output circuit is implemented on said single integrated circuit chip, and (d) an integrated circuit distributed output circuit generating the distributed response to at least one of the computer instructions stored by said integrated circuit read only memory.

Claim 20

A stored program data processor comprising: a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip; and an integrated circuit transfer circuit transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, wherein said integrated circuit transfer circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit transfer circuit includes (a) a first accessing circuit coupled to said integrated circuit read only memory and accessing a first byte of a triple byte transfer instruction, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to the first byte of the triple byte transfer instruction, (c) a second accessing circuit coupled to said integrated circuit read only memory and to said first transfer circuit and accessing a second byte and a third byte of the triple byte transfer instruction in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte accessed by said second accessing circuit, and (e) a transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address.

Claim 21

A stored program data processor comprising: a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip; and an integrated circuit transfer circuit transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, wherein said integrated circuit transfer circuit is implemented on said single integrated circuit chip, and wherein said integrated circuit transfer circuit includes (a) a first accessing circuit coupled to said integrated circuit read only memory and accessing a first byte of a triple byte transfer instruction, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to the first byte of the triple byte transfer instruction, (c) a second accessing circuit coupled to said integrated circuit read only memory and to said first transfer circuit and accessing a second byte and a third byte of the triple byte transfer instruction in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte accessed by said second accessing circuit, and (e) a transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address.

Claim 22

A stored program data processor as set forth in claim 19, further comprising an integrated circuit return address circuit coupled to said integrated circuit alterable memory and storing a return address in said integrated circuit alterable memory in response to the triple byte transfer instruction stored by said integrated circuit read only memory.

Claim 23

A stored program data processor as set forth in claim 19, further comprising an integrated circuit serial output circuit generating a serial output computer operand in response to at least one of the processor instructions stored by said integrated circuit read only memory, wherein said integrated circuit serial output circuit is implemented on said single integrated circuit chip.

Claim 24

A stored program data processor as set forth in claim 19, further comprising: an integrated circuit serial input circuit inputting a serial input operand in response to at least one of the processor instructions stored by said integrated circuit read only memory, wherein said integrated circuit serial input circuit is implemented on said single integrated circuit chip, and an integrated circuit alterable memory input circuit coupled to said integrated circuit alterable memory and to said integrated circuit serial input circuit and storing the serial input operand into said integrated circuit alterable memory in response to at least one of the processor instructions stored by said integrated circuit read only memory, wherein said integrated circuit alterable memory input circuit is implemented on said single integrated circuit chip.

Claim 25

A stored program data processor comprising: a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip, and wherein said integrated circuit processor includes (a) a first accessing circuit accessing a single byte instruction stored by said integrated circuit read only memory, (b) a first execution circuit executing the single byte instruction accessed by said first accessing circuit, (c) a second accessing circuit accessing a double byte instruction stored by said integrated circuit read only memory, (d) a second execution circuit executing the double byte instruction accessed by said second accessing circuit, (e) a third accessing circuit accessing a triple byte instruction stored by said integrated circuit read only memory, and (f) a third execution circuit executing the triple byte instruction accessed by said third accessing circuit.

Claim 26

A stored program data processor comprising: a single integrated circuit chip to implement said stored program data processor; an integrated circuit read only memory storing processor instructions, wherein said integrated circuit read only memory is implemented on said single integrated circuit chip; an integrated circuit alterable memory storing processed information, wherein said integrated circuit alterable memory is implemented on said single integrated circuit chip; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the information stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory, wherein said integrated circuit processor is implemented on said single integrated circuit chip, and wherein said integrated circuit processor includes (a) a first accessing circuit accessing a single byte instruction stored by said integrated circuit read only memory, (b) a first execution circuit executing the single byte instruction accessed by said first accessing circuit, (c) a second accessing circuit accessing a double byte instruction stored by said integrated circuit read only memory, (d) a second execution circuit executing the double byte instruction accessed by said second accessing circuit, (e) a third accessing circuit accessing a triple byte instruction stored by said integrated circuit read only memory, and (f) a third execution circuit executing the triple byte instruction accessed by said third accessing circuit.

Claim 27

A stored program data processor as set forth in claim 23, further comprising an integrated circuit serial output circuit generating a serial output operand in response to at least one of the processor instructions stored by said integrated circuit read only memory, wherein said integrated circuit serial output circuit is implemented on said single integrated circuit chip.

Claim 28

A stored program data processor system comprising: an input device generating input business information and a single chip integrated circuit data processor processing data in response to a stored program, said single chip integrated circuit data processor including (a) an integrated circuit read only main memory storing a program, wherein said integrated circuit read only main memory is included on said single chip; (b) an integrated circuit alterable memory storing operands, wherein said integrated circuit alterable memory is included on said single chip; (c) an integrated circuit input circuit generating a processor input signal in response to the input business information generated by said input device in response to the program stored in said integrated circuit read only main memory, wherein said integrated circuit input circuit is included on said single chip; (d) an integrated circuit storing circuit storing an operand into said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory and in response to the processor input signal generated by said integrated circuit input circuit, wherein said integrated circuit storing circuit is included on said single chip; (e) an integrated circuit processing circuit processing operands stored by said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory, wherein said integrated circuit processing circuit is included on said single chip; and (f) an integrated circuit output circuit outputting business information in response to the program stored by said integrated circuit read only main memory in response to the processing of operands by said integrated circuit processing circuit, wherein said integrated circuit output circuit is included on said single chip.

Claim 29

A stored program data processor system comprising: an input device generating input business information and a single chip integrated circuit data processor processing data in response to a stored program, said single chip integrated circuit data processor including (a) an integrated circuit read only main memory storing a program, wherein said integrated circuit read only main memory is included on said single chip; (b) an integrated circuit alterable memory storing operands, wherein said integrated circuit alterable memory is included on said single chip; (c) an integrated circuit input circuit generating a processor input signal in response to the input business information generated by said input device in response to the program stored in said integrated circuit read only main memory, wherein said integrated circuit input circuit is included on said single chip; (d) an integrated circuit storing circuit storing an operand into said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory and in response to the processor input signal generated by said integrated circuit input circuit, wherein said integrated circuit storing circuit is included on said single chip; (e) an integrated circuit processing circuit processing operands stored by said integrated circuit alterable memory in response to the program stored by said integrated circuit read only main memory, wherein said integrated circuit processing circuit is included on said single chip; and (f) an integrated circuit output circuit outputting business information in response to the program stored by said integrated circuit read only main memory in response to the processing of operands by said integrated circuit processing circuit, wherein said integrated circuit output circuit is included on said single chip.

Claim 30

A stored program data processor system as set forth in claim 19, wherein said integrated circuit output circuit is arranged to output the business information in serial form.

Claim 31

A computer system comprising: an input device generating a digital input signal; a single chip integrated circuit digital computer coupled to said input device and generating a digital output signal in response to the digital input signal generated by said input device, said single chip integrated circuit digital computer including: (a) an integrated circuit read only main memory included on said single chip and storing a computer program, (b) an integrated circuit alterable memory included on said single chip and storing computer operands, (c) an integrated circuit processing circuit included on said single chip and coupled to said integrated circuit alterable memory, to said integrated circuit read only memory, and to said input device and processing a computer operand stored by said integrated circuit alterable memory on the same chip in response to the computer program stored by said integrated circuit read only main memory on said single chip in response to the digital input signal, and (d) an integrated circuit output circuit included on said single chip and coupled to said integrated circuit read only memory and to said integrated circuit processing circuit and generating the digital output signal in response to the computer program stored by said integrated circuit read only main memory on said single chip and in response to the digital input signal responsive processing of a computer operand by said processing circuit on said single chip; and a process controller coupled to said integrated circuit output circuit and controlling a process in response to the digital output signal.

Claim 32

A computer system comprising: an input device generating a digital input signal; a single chip integrated circuit digital computer coupled to said input device and generating a digital output signal in response to the digital input signal generated by said input device, said single chip integrated circuit digital computer including: (a) an integrated circuit read only main memory included on said single chip and storing a computer program, (b) an integrated circuit alterable memory included on said single chip and storing computer operands, (c) an integrated circuit processing circuit included on said single chip and coupled to said integrated circuit alterable memory, to said integrated circuit read only memory, and to said input device and processing a computer operand stored by said integrated circuit alterable memory on the same chip in response to the computer program stored by said integrated circuit read only main memory on said single chip in response to the digital input signal, and (d) an integrated circuit output circuit included on said single chip and coupled to said integrated circuit read only memory and to said integrated circuit processing circuit and generating the digital output signal in response to the computer program stored by said integrated circuit read only main memory on said single chip and in response to the digital input signal responsive processing of a computer operand by said processing circuit on said single chip; and a process controller coupled to said integrated circuit output circuit and controlling a process in response to the digital output signal.

Claim 33

A computer system as set forth in claim 27, wherein said integrated circuit output circuit is adapted to generate the digital output signal as a serial digital output signal.

Claim 34

A computer on a chip comprising: an integrated circuit chip having a computer implemented thereon; an integrated circuit main memory storing computer instructions, wherein said integrated circuit main memory is included on said integrated circuit chip; an integrated circuit operand memory storing operands, wherein said integrated circuit operand memory is included on said integrated circuit chip; and an integrated circuit processing circuit processing the operands stored by said integrated circuit operand memory in response to the instructions stored by said integrated circuit main memory, wherein said processing circuit is included on said integrated circuit chip.

Claim 35

A computer on a chip comprising: an integrated circuit chip having a computer implemented thereon; an integrated circuit main memory storing computer instructions, wherein said integrated circuit main memory is included on said integrated circuit chip; an integrated circuit operand memory storing operands, wherein said integrated circuit operand memory is included on said integrated circuit chip; and an integrated circuit processing circuit processing the operands stored by said integrated circuit operand memory in response to the instructions stored by said integrated circuit main memory, wherein said processing circuit is included on said integrated circuit chip.

Claim 36

A computer on a chip as set forth in claim 29, wherein said integrated circuit main memory includes an integrated circuit read only memory storing the instructions in read only form.

Claim 37

A computer on a chip as set forth in claim 29, wherein said integrated circuit operand memory includes an integrated circuit random access memory storing the operands in random access form.

Claim 38

A computer on a chip as set forth in claim 29, further comprising at least one additional integrated circuit chip; wherein said additional integrated circuit chip includes additional memory coupled to extend said integrated circuit main memory on said computer integrated circuit chip and storing additional computer instructions.

Claim 39

A computer on a chip as set forth in claim 29, further comprising at least one additional integrated circuit chip; wherein said additional integrated circuit chip includes an interface circuit coupled to said computer integrated circuit chip and transferring information between said integrated circuit chip and an external device.

Claim 40

A computer on a chip as set forth in claim 29, further comprising: an integrated circuit output circuit coupled to said integrated circuit processing circuit and generating a display output signal, wherein said integrated circuit operand memory is included on said integrated circuit chip, and an operator display coupled to said integrated circuit output circuit and displaying information in response to the display output signal.

Claim 41

A computer on a chip as set forth in claim 29, further comprising an integrated circuit serial output circuit generating a serial output operand in response to at least one of the computer instructions stored by said integrated circuit main memory, wherein said serial output circuit is included on said chip.

Claim 42

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; an integrated circuit interrupt input logic circuit generating an interrupt input signal; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit interrupt logic circuit and accessing an interrupt instruction stored by said integrated circuit read only memory in response to the interrupt input signal; and an integrated circuit interrupt return logic circuit coupled to said integrated circuit alterable memory and to said integrated circuit interrupt input logic circuit and storing a return address in said integrated circuit alterable memory in response to the interrupt input signal.

Claim 43

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; an integrated circuit interrupt input logic circuit generating an interrupt input signal; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit interrupt logic circuit and accessing an interrupt instruction stored by said integrated circuit read only memory in response to the interrupt input signal; and an integrated circuit interrupt return logic circuit coupled to said integrated circuit alterable memory and to said integrated circuit interrupt input logic circuit and storing a return address in said integrated circuit alterable memory in response to the interrupt input signal.

Claim 44

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, said integrated circuit transfer logic circuit including (a) a first accessing circuit accessing a first byte of a triple byte transfer instruction stored by said integrated circuit read only memory, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to said first byte of a triple byte transfer instruction, (c) a second accessing circuit coupled to said first transfer circuit and accessing a second byte and a third byte of a triple byte transfer instruction stored by said integrated circuit read only memory in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte of a triple byte transfer instruction, and (f) a second transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address.

Claim 45

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and generating the computer operands stored by said integrated circuit alterable memory in response to the instructions stored by said integrated circuit read only memory; an integrated circuit transfer logic circuit coupled to said integrated circuit read only memory and transferring instruction control in response to a triple byte transfer instruction stored by said integrated circuit read only memory, said integrated circuit transfer logic circuit including (a) a first accessing circuit accessing a first byte of a triple byte transfer instruction stored by said integrated circuit read only memory, (b) a first transfer circuit coupled to said first accessing circuit and generating a transfer signal in response to said first byte of a triple byte transfer instruction, (c) a second accessing circuit coupled to said first transfer circuit and accessing a second byte and a third byte of a triple byte transfer instruction stored by said integrated circuit read only memory in response to the transfer signal, (d) a combining circuit coupled to said second accessing circuit and generating a double byte transfer address by combining said second byte and said third byte of a triple byte transfer instruction, and (f) a second transfer circuit coupled to said combining circuit and transferring instruction control in response to the double byte transfer address.

Claim 46

An integrated circuit stored program computer as set forth in claim 37, further comprising an integrated circuit return address circuit coupled to said integrated circuit transfer logic circuit and storing a return address in said integrated circuit alterable memory in response to the transferring of instruction control by said integrated circuit transfer logic circuit.

Claim 47

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes (a) a first accessing logic circuit accessing a single byte computer instruction stored by said integrated circuit read only memory, (b) a first instruction execution logic circuit coupled to said first accessing logic circuit and executing the single byte computer instruction accessed by said first accessing logic circuit, (c) a second accessing logic circuit accessing the double byte computer instruction stored by said integrated circuit read only memory, (d) a second instruction execution logic circuit coupled to said second accessing logic circuit and executing the double byte computer instruction accessed by said second accessing logic circuit, (e) a third accessing logic circuit accessing a triple byte computer instruction stored by said integrated circuit read only memory, and (f) a third instruction execution logic circuit coupled to said third accessing logic circuit and executing the triple byte computer instruction accessed by said third accessing logic circuit.

Claim 48

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes (a) a first accessing logic circuit accessing a single byte computer instruction stored by said integrated circuit read only memory, (b) a first instruction execution logic circuit coupled to said first accessing logic circuit and executing the single byte computer instruction accessed by said first accessing logic circuit, (c) a second accessing logic circuit accessing the double byte computer instruction stored by said integrated circuit read only memory, (d) a second instruction execution logic circuit coupled to said second accessing logic circuit and executing the double byte computer instruction accessed by said second accessing logic circuit, (e) a third accessing logic circuit accessing a triple byte computer instruction stored by said integrated circuit read only memory, and (f) a third instruction execution logic circuit coupled to said third accessing logic circuit and executing the triple byte computer instruction accessed by said third accessing logic circuit.

Claim 49

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; and an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes an inline logic circuit executing an inline instruction, said inline logic circuit including: (1) a first accessing logic circuit accessing an inline computer instruction byte stored by said integrated circuit read only memory, (2) a first execution logic circuit coupled to said first accessing logic circuit and generating an inline signal in response to an inline computer instruction byte accessed by ,said first accessing logic circuit, (3) a second accessing logic circuit coupled to said first execution logic circuit and accessing at least one inline operand byte stored by said integrated circuit read only memory in response to the inline signal, and (4) a second execution logic circuit coupled to said second accessing logic circuit and processing the at least one inline operand byte accessed by said second accessing logic circuit.

Claim 50

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; and an integrated circuit processing logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory, wherein said integrated circuit processing logic circuit includes an inline logic circuit executing an inline instruction, said inline logic circuit including: (1) a first accessing logic circuit accessing an inline computer instruction byte stored by said integrated circuit read only memory, (2) a first execution logic circuit coupled to said first accessing logic circuit and generating an inline signal in response to an inline computer instruction byte accessed by ,said first accessing logic circuit, (3) a second accessing logic circuit coupled to said first execution logic circuit and accessing at least one inline operand byte stored by said integrated circuit read only memory in response to the inline signal, and (4) a second execution logic circuit coupled to said second accessing logic circuit and processing the at least one inline operand byte accessed by said second accessing logic circuit.

Claim 51

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; and an integrated circuit indirect transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and providing indirect transfer of program control, said indirect transfer means including: (1) a first accessing logic circuit accessing an indirect transfer computer instruction stored by said integrated circuit read only memory, (2) an indirect transfer logic circuit coupled to said first accessing logic circuit and generating an indirect transfer signal in response to an indirect transfer computer instruction accessed by said first accessing logic circuit, (3) a second accessing logic circuit coupled to said indirect transfer logic circuit and accessing an indirect transfer address stored by said integrated circuit alterable memory in response to the indirect transfer signal, and (4) a third accessing logic circuit coupled to said second accessing logic circuit and accessing an instruction stored by said integrated circuit read only memory in response to the indirect transfer address accessed by said second accessing logic circuit.

Claim 52

An integrated circuit stored program computer comprising: an integrated circuit read only memory storing computer instructions; an integrated circuit alterable memory storing computer operands; an integrated circuit processor coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and processing the computer operands stored by said integrated circuit alterable memory in response to the computer instructions stored by said integrated circuit read only memory; and an integrated circuit indirect transfer logic circuit coupled to said integrated circuit read only memory and to said integrated circuit alterable memory and providing indirect transfer of program control, said indirect transfer means including: (1) a first accessing logic circuit accessing an indirect transfer computer instruction stored by said integrated circuit read only memory, (2) an indirect transfer logic circuit coupled to said first accessing logic circuit and generating an indirect transfer signal in response to an indirect transfer computer instruction accessed by said first accessing logic circuit, (3) a second accessing logic circuit coupled to said indirect transfer logic circuit and accessing an indirect transfer address stored by said integrated circuit alterable memory in response to the indirect transfer signal, and (4) a third accessing logic circuit coupled to said second accessing logic circuit and accessing an instruction stored by said integrated circuit read only memory in response to the indirect transfer address accessed by said second accessing logic circuit.