US3602901A
Expired / Lapsed
US
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Circuit for controlling the loading and editing of information in a recirculating memory
Assignee: BUNKO RAMO CORP
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Filing: 1969-10-31
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Granted: 1971-08-31
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Expires: 1989-10-31
Abstract
Abstract A circuit for controlling the loading and editing of information in a recirculating memory. A coded input character is converted, in a suitable encoding circuit, into a multibit coded instruction. A first group of bits in the instruction are utilized to control the location in the memory at which the execution of the instruction begins, a second group of bits in the instruction are utilized to control the location in the memory at which the execution of the instruction ends, and a third group of bits in the instruction are utilized to control the action performed on information during the execution of the instruction. A fourth group of bits in the instruction may be utilized to control the character position in the memory at which an entry marker is stored when the execution of the instruction is completed.
Inventors
- 👤 Dixson Teh-Chao Jen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:36
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/3004; G06F9/30043; G06F40/00; G06F40/10; G06F40/12; G06F40/123
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
114 words
A circuit for controlling the loading and editing of information in a recirculating memory comprising: means for applying a coded input character to said circuit; means responsive to said input character for generating a coded multibit instruction; means responsive to a first selected group of said instruction bits for controlling the location in said memory at which the execution of said instruction begins; means responsive to a second selected group of said instruction bits for controlling the location in said memory at which the execution of said instruction ends; and means responsive to a third selected group of said instruction bits for controlling the action performed on information during the execution of said instruction.
Claim 2
Dependent Claim
114 words
A circuit for controlling the loading and editing of information in a recirculating memory comprising: means for applying a coded input character to said circuit; means responsive to said input character for generating a coded multibit instruction; means responsive to a first selected group of said instruction bits for controlling the location in said memory at which the execution of said instruction begins; means responsive to a second selected group of said instruction bits for controlling the location in said memory at which the execution of said instruction ends; and means responsive to a third selected group of said instruction bits for controlling the action performed on information during the execution of said instruction.
Claim 3
Dependent Claim
72 words
A circuit of the type described in claim 1 wherein information is stored in said memory in character positions with an entry marker being stored in the character position in which the next input character would normally be stored; and including means responsive to a fourth selected group of said instruction bits for controlling the character position in which said entry marker is stored when the execution of said instruction is completed.
Claim 4
Dependent Claim
18 words
A circuit of the type described in claim 1 wherein said instruction generating means is a read-only memory.
Claim 5
Dependent Claim
37 words
A circuit of the type described in claim 1 wherein there are a plurality of said instruction generating means; and including means for selecting the instruction generating means to which a given input character will be applied.
Claim 6
Dependent Claim
24 words
A circuit of the type described in claim 4 wherein each of said instruction generating means is responsive to a different input code type.
Claim 7
Dependent Claim
48 words
A circuit of the type described in claim 1 wherein each of said means responsive to a selected group of instruction bits including decoder means, and means responsive to each output from the decoder means for generating the desired output at the appropriate time in the memory cycle.
Claim 8
Dependent Claim
54 words
A circuit of the type described in claim 6 wherein said decoder output responsive means includes a plurality of gating means, each of which has as one input a corresponding output from the decoder means, and, as the other input, a signal representing the selected condition, information, or time, represented by the decoder output.
Claim 9
Dependent Claim
68 words
A circuit of the type described in claim 1 wherein said begin location controlling means and said end location controlling means include a bistable means which is set when the selected begin location is detected and is reset when the selected end location is detected, and means responsive to said bistable means being in its set condition for permitting the loading or editing of information in said memory.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-08-30 | 1975-03-01 | 1975-08-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-08-30 | 1979-03-01 | 1979-08-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-08-30 | 1983-03-01 | 1983-08-31 | $7700.00 | Window Closed / Lapsed |