US4394726A
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Distributed multiport memory architecture
Assignee: United States, AS REPRESENTED BY NATIONAL AERONAUTICS AND SPCAE ADMINISTRATION
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Filing: 1981-04-29
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Granted: 1983-07-19
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Expires: 2001-04-29
Abstract
Abstract A multiport memory architecture is disclosed for each of a plurality of task centers (11, 20, 30, 40) connected to a command and data bus (10). Each task center, (such as the center 11) includes a memory (13) and a plurality of devices (12, 14, 15, 17) which request direct memory access as needed. The memory (13) includes an internal data bus (53) and an internal address bus (50) to which the devices are connected, and direct timing and control logic (54) comprised of a 10-state ring counter (62) for allocating memory devices by enabling AND gates (64) connected to the request signal lines of the devices. The outputs of AND gates connected to the same device are combined by OR gates (66) to form an acknowledgement signal that enables the devices to address the memory during the next clock period. The length of the ring counter may be effectively lengthened to any multiple of ten to allow for more direct memory access intervals in one repetitive sequence. One device is a network bus adapter (14) which serially shifts onto the command and data bus (10) a data word (8 bits plus control and parity bits) during the next ten direct memory access intervals after it has been granted access. The NBA is therefore allocated only one access in every ten intervals, which is a predetermined interval for all centers. The ring counters of all centers are periodically synchronized by DMA SYNC signal to assure that all NBAs be able to function in synchronism for data transfer from one center to another.
Inventors
- 👤 Wayne H. Kohl
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:07
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/28; G06F13/287; G06F13/16; G06F13/18
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
215 words
In a distributed data processing system having a plurality of independent centers connected to a bus for performing tasks, and having a source of system clock pulses applied to all centers, each task center being comprised of a memory and a plurality of devices using said memory, one of said devices in each center being a bus adapter coupling said bus to said memory, and one of said devices in one of said centers being a bus controller for control of the transfer of data between task centers, a separate multiport memory architecture for said memory of each task center comprising logic means responsive to said clock pulses for synchronous timing and control of direct access to said memory by devices of the task center, including said bus adapter, a separate device being given access during each of NX clock pulse periods in a predetermined sequence, with selected devices being given access more than once in a sequence, where N is the fixed number of bits in a word to be serially transferred on said bus between centers and X is an integer selected for each task center to satisfy particular needs of the task center, whereby all devices of a task center are given memory access at least once during NX clock pulse intervals.
Claim 2
Dependent Claim
215 words
In a distributed data processing system having a plurality of independent centers connected to a bus for performing tasks, and having a source of system clock pulses applied to all centers, each task center being comprised of a memory and a plurality of devices using said memory, one of said devices in each center being a bus adapter coupling said bus to said memory, and one of said devices in one of said centers being a bus controller for control of the transfer of data between task centers, a separate multiport memory architecture for said memory of each task center comprising logic means responsive to said clock pulses for synchronous timing and control of direct access to said memory by devices of the task center, including said bus adapter, a separate device being given access during each of NX clock pulse periods in a predetermined sequence, with selected devices being given access more than once in a sequence, where N is the fixed number of bits in a word to be serially transferred on said bus between centers and X is an integer selected for each task center to satisfy particular needs of the task center, whereby all devices of a task center are given memory access at least once during NX clock pulse intervals.
Claim 3
Dependent Claim
50 words
In a distributed data processing system as defined in claim 1 having a source of synchronizing pulses occurring at intervals of some multiple of NX clock pulses for the task center having the largest number X, wherein said direct memory access and control means is resynchronized by said synchronizing pulses.
Claim 4
Dependent Claim
68 words
The improvement defined by claim 2 wherein said network bus adapter of each task center is given access by said logic means once during every group of N clock pulses in order for said bus controller to direct a serial N-bit word transfer from one center to one or more centers during every group of N clock pulses which thereby define a serial word time on said bus.
Claim 5
Dependent Claim
39 words
A system as defined in claim 1, 2, or 3 wherein said center having said bus controller includes a command interface means as a device coupled to said memory for storing in said memory commands from an external source.
Claim 6
Dependent Claim
73 words
A system as defined in claim 4 wherein said multiport memory structure includes an internal address bus and an internal data bus, and each of said devices is coupled to said internal address bus for addressing said memory and each of said devices is coupled to said internal data bus for reading out or storing data in said memory when enabled to do so by said direct memory access timing and control means.
Claim 7
Dependent Claim
35 words
A system as defined in claim 5 wherein a device is enabled by said direct memory access timing and control means during its allotted clock pulse interval upon request by a signal acknowledging the request.
Claim 8
Dependent Claim
186 words
A system as defined in claim 6 wherein said direct memory access timing and control means of each is comprised of an array of NX AND gates, an array of OR gates, one OR gate for each device of a center, a ring counter means responsive to said clock pulses and resynchronized by said synchronizing pulses for successively enabling said array of NX AND gates, each AND gate having one terminal connected to a different one of NX output terminals of said ring counter means and the other input terminal conected to receive a request signal from a device, some AND gates having the other input terminal connected to the same devices as desired, each OR gate being connected to pass the output signal of all AND gates connected to receive a memory access request signal from the same associated device, each OR gate having its output terminal connected to the associated device to acknowledge the memory access request and enable the associated device to place a memory address on said internal address bus, and to read or write in memory through said internal data bus.
Claim 9
Dependent Claim
156 words
A multiport memory comprised of a memory into which data may be stored, and from which data stored may be read out, a bus for data stored and read from said memory, a bus for addressing said memory for storing or reading data, a plurality of devices connected to said address bus and said data bus for access to said memory to read or store, or both read and store data, each device being adapted to generate a request signal when memory access is required, and direct memory access timing and control means for allocating memory access to said devices in a fixed periodic sequence and acknowledging a request by each device during its allocated intervals by an acknowledgement signal to the device requesting access, thereby to enable it to place an address on said address bus and place or accept data on or from said data bus for storing or reading data from said memory.
Claim 10
Dependent Claim
156 words
A multiport memory comprised of a memory into which data may be stored, and from which data stored may be read out, a bus for data stored and read from said memory, a bus for addressing said memory for storing or reading data, a plurality of devices connected to said address bus and said data bus for access to said memory to read or store, or both read and store data, each device being adapted to generate a request signal when memory access is required, and direct memory access timing and control means for allocating memory access to said devices in a fixed periodic sequence and acknowledging a request by each device during its allocated intervals by an acknowledgement signal to the device requesting access, thereby to enable it to place an address on said address bus and place or accept data on or from said data bus for storing or reading data from said memory.
Claim 11
Dependent Claim
169 words
A multiport memory as defined in claim 8 wherein said direct memory access timing and control means is comprised of a source of clock pulses, a ring counter means responsive to said clock pulses for producing at output terminals thereof output signals in repetitive sequence, an array of AND gates, one for each output terminal of said ring counter means, each AND gate having one terminal connected to a different one of said output terminals of said ring counter means, and the other input terminal connected to receive a request signal from a device, some AND gates having the other input terminal connected to the same devices as desired, and an array of OR gates, one OR gate for each device, each OR gate being connected to pass the output signal of all AND gates connected to receive a memory access signal from the same associated device, each OR gate having its output terminal connected to the associated device to transmit the passed request signal as an acknowledgement signal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-07-18 | 1987-01-17 | 1987-07-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-07-18 | 1991-01-17 | 1991-07-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-07-18 | 1995-01-17 | 1995-07-19 | $7700.00 | Window Closed / Lapsed |