Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
116 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adaptive, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: means for generating a derived instruction as a composite function of the original instruction and dynamic operational parameters by replacing bits in the original instruction; and means to execute said derived instruction.
Claim 2
Dependent Claim
116 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adaptive, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: means for generating a derived instruction as a composite function of the original instruction and dynamic operational parameters by replacing bits in the original instruction; and means to execute said derived instruction.
Claim 3
Dependent Claim
117 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adaptive, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: means for generating a derived instruction as a composite function of the original instruction and dynamic operational parameters by inserting a bit into the original instruction; and means to execute said derived instruction.
Claim 4
Dependent Claim
117 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adaptive, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: means for generating a derived instruction as a composite function of the original instruction and dynamic operational parameters by inserting a bit into the original instruction; and means to execute said derived instruction.
Claim 5
Dependent Claim
243 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to a significant number of processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adpative, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: spatial dependent status means (77) coupled for receiving said original instruction for providing a first signal indicative of a spatial dependent status operational parameter at a first node; execution means, including the processing means (72), to execute the derived instruction and to provide a result to the output means and also to provide a second signal indicative of a data dependent status operational parameter at a second node; dependence select and verify means (78), coupled for receiving said original instruction and coupled to said first node and said second node for receiving said first signal and said second signal for deriving at a third node an instruction as a composite function of said original instruction, said first signal and said second signal; and instruction modification and extension means (79), coupled for receiving said original instruction and coupled to said third node for receiving the composite instruction for providing said derived instruction to the processing means.
Claim 6
Dependent Claim
243 words
An array processor having a control unit with instruction issuing capability and having an array of individual processing elements for processing data according to instructions applied simultaneously to a significant number of processing elements by the control unit, each processing element having input means, processing means, and output means connected to other processing elements characterized in that each of the processing elements is adpative, in that each adaptive processing element receives an original instruction, generates a derived instruction and executes the derived instruction, each adaptive processing element comprising: spatial dependent status means (77) coupled for receiving said original instruction for providing a first signal indicative of a spatial dependent status operational parameter at a first node; execution means, including the processing means (72), to execute the derived instruction and to provide a result to the output means and also to provide a second signal indicative of a data dependent status operational parameter at a second node; dependence select and verify means (78), coupled for receiving said original instruction and coupled to said first node and said second node for receiving said first signal and said second signal for deriving at a third node an instruction as a composite function of said original instruction, said first signal and said second signal; and instruction modification and extension means (79), coupled for receiving said original instruction and coupled to said third node for receiving the composite instruction for providing said derived instruction to the processing means.
Claim 7
Dependent Claim
83 words
An array processor according to claim 3, in which said spatial dependent status means (77) comprises a processor identification register (81); in which said processing means (72) comprises data dependent status register means; and in which said instruction modification and extension means (79) is coupled to said processing means (72) to provide processing activity which is a composite function of said original instruction and the data content of said processor identification register and the data content of said data dependent status register means.
Claim 8
Dependent Claim
75 words
An array processor according to claim 3, wherein said spatial dependent status means comprises: a processor identification register (81) and a shift register (82); and wherein said dependence select and verify means (78) comprises a template register (84) and an agreement verifier (85), whereby said processor identification register, said shift register and said agreement verifier serve as a movable window for providing bits for controlling generation of the derived instruction by the adaptive processing element.
Claim 9
Dependent Claim
55 words
An array processor according to claim 3, wherein said spatial dependent status means comprises: a processor identification register (81') divided into sections 1 . . . K-1, K and a shift register means (92) similarly divided into sections 1 . . . K-1, K and interconnected section by section with said processor identification register (81').
Claim 10
Dependent Claim
47 words
An array processor according to claim 3, wherein said dependence select and verify means comprises a plurality of multiplexers arrayed to provide as an output agreement bit values as a composite function of said original instruction and data values to said instruction modification and extension means (79).