Abstract This disclosure relates to a programmable unit employing plural levels of sub-instruction sets in addition to conventional instruction sets. The conventional level of instruction sets is employed to specify computational routines and other processing algorithms to be carried out by the unit. Each instruction in a conventional set is implemented in the unit by a sequence of first level sub-instructions which specify the various operations to be carried out within the unit which operations are comprised within the specific routine. In turn, the various first level sub-instructions are implemented by second level sub-instructions which specify the various control signals required to set the various gates as required for the particular unit operation to be carried out. With this hierarchy of sub-instruction sets, first level sub-instruction sets may be interchanged dynamically during the operation of the unit to dynamically change the processing capability of the unit. This eliminates the requirement for any special logic circuitry to accommodate particular computational routines and allows the arithmetic logic unit to be designed as multiples of the basic logic unit in accordance with particular desired data path widths. A manner is disclosed by which the interchanging of first level sub-instruction sets provides for placing the unit in different control modes such as input-output control or processing control. A manner is also disclosed by which interchanging of different first level sub-instruction sets accommodates the execution of programs written in different program language forms.
A microinstruction controllable processor comprising: a program memory containing a series of microprograms, each microprogram containing a set of microinstructions; means for addressing said program memory to provide an operative microprogram; means controlled by said operative microprogram for sequentially providing operative microinstructions from the set of microinstructions associated with said addressed microprogram; means for writing microprograms into said program memory of selected address locations therein; and means controlled by a processor control field of said provided operative microinstruction for providing signals to control the processor; said program memory addressing means including a second memory separate from said program memory the individual words of which are selected by said program memory and communicated to said program memory addressing means under control of a provided operative microinstruction; and means controlled by said operative microinstruction for enabling said program memory write means so as to selectively change certain ones of said microprograms.
Claim 2
Dependent Claim
149 words
A microinstruction controllable processor comprising: a program memory containing a series of microprograms, each microprogram containing a set of microinstructions; means for addressing said program memory to provide an operative microprogram; means controlled by said operative microprogram for sequentially providing operative microinstructions from the set of microinstructions associated with said addressed microprogram; means for writing microprograms into said program memory of selected address locations therein; and means controlled by a processor control field of said provided operative microinstruction for providing signals to control the processor; said program memory addressing means including a second memory separate from said program memory the individual words of which are selected by said program memory and communicated to said program memory addressing means under control of a provided operative microinstruction; and means controlled by said operative microinstruction for enabling said program memory write means so as to selectively change certain ones of said microprograms.