US4344134A
Expired / Lapsed
US
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Partitionable parallel processor
Assignee: Unisys Corp
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Filing: 1980-06-30
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Granted: 1982-08-10
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Expires: 2000-06-30
Abstract
Abstract In a parallel processing array wherein each processor therein issues a ready signal to signify that it is ready to begin a parallel processing task and initiates the task upon receipt of an initiate signal the parallel processing array is rendered partitionable into parallel processing subarrays by a control node tree having a plurality of control nodes connected to the plurality of processors and in decreasing levels to each other in a tree-like fashion down to a single root node. Each node is controlled to function as a non-root wherein it receives a ready signal from its processor side and passes it along toward the single root node or as a root node whereupon receiving a ready signal it issues back an initiate signal toward the plurality of processors.
Inventors
- 👤 George H. Barnes
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 03:02
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
356 words
A partitionable parallel processor control network for a plurality of parallel processors wherein each processor therein emits a ready signal when it is ready to execute a parallel processing task and initiates said parallel processing task upon receipt of an initiate signal, said partitionable parallel processor control network comprising: a single root control node means having a plurality of processor side data lines for receiving on each a ready signal and sending back on each an initiate signal when each processor side data line in said plurality thereof is receiving a ready signal; a control node tree having a plurality of bi-mode control node means, each bi-mode control node means therein having a plurality of processor side data lines, a single root control node means side data line, and a control input for designating a non-root operating mode wherein a ready signal is outputted on said signal root control node means side data line when a ready signal is being received on each processor side data line in said plurality thereof, and for designating a root operating mode wherein an initiate signal is outputted back on each processor side data line in said plurality thereof when a ready signal is being received on each processor side data line in said plurality thereof, said control node tree being configured with a first level and a lesser level of pluralities of bi-mode control node means, each said first level bi-mode control node means therein having each processor side data line in its said plurality thereof connected to an individual processor in said plurality thereof for receiving therefrom a ready signal and for sending thereto an initiate signals, said first level plurality and lesser level pluralities of bi-mode control node means being coupled in a tree-like fashion to a last level bi-mode control node means therein having each said root side data line thereof connected to an individually associated processor side data line of said single root control node means; and designating means connected to said control input of each bi-mode control node means for designating an operating mode means of each bi-mode control node in said plurality thereof.
Claim 2
Dependent Claim
356 words
A partitionable parallel processor control network for a plurality of parallel processors wherein each processor therein emits a ready signal when it is ready to execute a parallel processing task and initiates said parallel processing task upon receipt of an initiate signal, said partitionable parallel processor control network comprising: a single root control node means having a plurality of processor side data lines for receiving on each a ready signal and sending back on each an initiate signal when each processor side data line in said plurality thereof is receiving a ready signal; a control node tree having a plurality of bi-mode control node means, each bi-mode control node means therein having a plurality of processor side data lines, a single root control node means side data line, and a control input for designating a non-root operating mode wherein a ready signal is outputted on said signal root control node means side data line when a ready signal is being received on each processor side data line in said plurality thereof, and for designating a root operating mode wherein an initiate signal is outputted back on each processor side data line in said plurality thereof when a ready signal is being received on each processor side data line in said plurality thereof, said control node tree being configured with a first level and a lesser level of pluralities of bi-mode control node means, each said first level bi-mode control node means therein having each processor side data line in its said plurality thereof connected to an individual processor in said plurality thereof for receiving therefrom a ready signal and for sending thereto an initiate signals, said first level plurality and lesser level pluralities of bi-mode control node means being coupled in a tree-like fashion to a last level bi-mode control node means therein having each said root side data line thereof connected to an individually associated processor side data line of said single root control node means; and designating means connected to said control input of each bi-mode control node means for designating an operating mode means of each bi-mode control node in said plurality thereof.
Claim 3
Dependent Claim
56 words
The partitionable parallel processor control network according to claim 1 wherein each bi-mode control node means in said plurality thereof includes: means for introducing a relatively slight delay after receiving a ready signal on each processor side data line in said plurality thereof before outputting said initiate signal thereon when operating in said root operating mode.
Claim 4
Dependent Claim
44 words
The partitionable parallel processor control network according to claim 1 or claim 2 wherein said control node tree is configurated in substantially a geometric progression of said bi-mode control node means proceeding from said single root node means to said plurality of parallel processors.
Claim 5
Dependent Claim
48 words
The partitionable parallel processor according to claim 1 or claim 2 wherein each bi-mode control node means in said plurality thereof includes a flip-flop settable by said control input to either of two states corresponding to said designated non-root operating mode and to said designated root operating mode.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-08-09 | 1986-02-08 | 1986-08-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-08-09 | 1990-02-08 | 1990-08-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-08-09 | 1994-02-08 | 1994-08-10 | $7700.00 | Window Closed / Lapsed |