US3886524A
Expired / Lapsed
US
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Asynchronous communication bus
Assignee: Texas Instruments Inc
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Filing: 1973-10-18
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Granted: 1975-05-27
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Expires: 1993-10-18
Abstract
Abstract An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are shared between all of said devices. A logic circuit in each said master device is connected to each of three signal lines common to all logic circuits in all of said master devices. One of the three lines is connected in series in the order of assigned priority between master devices. Means are provided to actuate the logic circuits via the three signal lines to limit access to said bus in the order of assigned priority and to signal to other master units bus availability and to transmit an access granted signal to master units down stream of a user unit with only one logic gate delay per downstream unit.
Inventors
- 👤 Daren R Appelt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 21:06
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/37; G06F13/38; G06F13/42; G06F13/4204; G06F13/4208; G06F13/4213
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
135 words
An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are time shared by all of said devices, which comprises: a. a logic circuit in each said master device b. three signal lines common to all of said logic circuits in all of said master devices with one of said lines connected in series in the order of assigned priority between said master devices and the other two lines connecting said logic circuits in parallel. c. means in each said master device to actuate each said logic circuit to limit access to said bus in the order of said priority and to signal availability status of said bus tO all of said master devices.
Claim 2
Dependent Claim
135 words
An asynchronous bus for self-determined priority of communication among master computer devices communicating with slave devices through said bus where a multi bit data channel and a multi bit address channel are time shared by all of said devices, which comprises: a. a logic circuit in each said master device b. three signal lines common to all of said logic circuits in all of said master devices with one of said lines connected in series in the order of assigned priority between said master devices and the other two lines connecting said logic circuits in parallel. c. means in each said master device to actuate each said logic circuit to limit access to said bus in the order of said priority and to signal availability status of said bus tO all of said master devices.
Claim 3
Dependent Claim
16 words
The system of claim 1 wherein the logic circuit in all said master units is identical.
Claim 4
Dependent Claim
33 words
The system of claim 1 wherein said one of said lines includes a single logic gate in each master device thereby limiting the signal delay to one logic gate interval per master device.
Claim 5
Dependent Claim
57 words
An asynchronous bus apparatus for self-determining priority among a plurality of master computer devices each communicating with one or more slave devices through said bus, comprising: a. a like logic circuit in each said master device; and b. means to actuate each said logic circuit for assigning priority among master devices to limit access to said bus.
Claim 6
Dependent Claim
57 words
An asynchronous bus apparatus for self-determining priority among a plurality of master computer devices each communicating with one or more slave devices through said bus, comprising: a. a like logic circuit in each said master device; and b. means to actuate each said logic circuit for assigning priority among master devices to limit access to said bus.
Claim 7
Dependent Claim
29 words
Asynchronous bus apparatus as set forth in claim 4, wherein: a. said priority assigning means includes three signal lines of said bus common to all of said logic circuits.
Claim 8
Dependent Claim
27 words
The combination of claim 5 in which one of said three signal lines is connected in series in the order of assigned priority between said master devices.
Claim 9
Dependent Claim
38 words
The combination of claim 2 wherein one of said three signal lines is linked to said master devices by a single logic gate per master device thereby limiting signal delay to one logic gate interval per master device.
Claim 10
Dependent Claim
106 words
In a data processing system where information including data and instruction words are to be transferred over a communication bus from a plurality of units, the combination which comprises: a. means for connecting all of said units in series along a control logic line in said bus in the order of assigned priority among said units, b. means in at least one said unit to generate an access granted signal when said unit uses said bus, and c. means in at least one said unit to transmit said signal to other units downstream of said user unit with only one logic gate delay per downstream unit.
Claim 11
Dependent Claim
106 words
In a data processing system where information including data and instruction words are to be transferred over a communication bus from a plurality of units, the combination which comprises: a. means for connecting all of said units in series along a control logic line in said bus in the order of assigned priority among said units, b. means in at least one said unit to generate an access granted signal when said unit uses said bus, and c. means in at least one said unit to transmit said signal to other units downstream of said user unit with only one logic gate delay per downstream unit.
Claim 12
Dependent Claim
76 words
In the operation of a bus interconnecting a plurality of master units vying for access to said bus for transfer of multi bit data and instruction words, the combination which comprises: a. like arbitration logic means in each master unit; b. means at each said unit, operatively connected to said logic means, for generating an access granted signal; and c. means to apply said signal to said bus from the unit gaining access to said bus.
Claim 13
Dependent Claim
76 words
In the operation of a bus interconnecting a plurality of master units vying for access to said bus for transfer of multi bit data and instruction words, the combination which comprises: a. like arbitration logic means in each master unit; b. means at each said unit, operatively connected to said logic means, for generating an access granted signal; and c. means to apply said signal to said bus from the unit gaining access to said bus.
Claim 14
Dependent Claim
39 words
The combination set forth in claim 9 in which each said unit includes a decision logic means, each said decision logic means including a single logic gate to limit the signal delay to one logic gate delay per unit.
Claim 15
Independent Claim
101 words
The method of information transfer between units of multi bit capability over a multichannel bus, the method which comprises: a. connecting all said master units in series on one line of said bus in the order of assigned priorities between said units, b. generating an access request signal at each master unit connected to said bus when access is sought, c. generating an access granted signal by the unit of highest priority among units seeking access to said bus, and d. transmitting said access granted signal to units down the priority stream with only one logic gate delay per downstream unit.
Claim 16
Independent Claim
101 words
The method of information transfer between units of multi bit capability over a multichannel bus, the method which comprises: a. connecting all said master units in series on one line of said bus in the order of assigned priorities between said units, b. generating an access request signal at each master unit connected to said bus when access is sought, c. generating an access granted signal by the unit of highest priority among units seeking access to said bus, and d. transmitting said access granted signal to units down the priority stream with only one logic gate delay per downstream unit.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1978-05-26 | 1978-11-25 | 1979-05-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1982-05-26 | 1982-11-25 | 1983-05-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1986-05-26 | 1986-11-25 | 1987-05-27 | $7700.00 | Window Closed / Lapsed |