Image analyzer with common data/instruction bus

Claim 3

The system of claim 1 wherein each stage includes input and output data control lines as well as input and output command control lines; said data and command output lines of one stage being connected to the data and command input lines of the next stage in the pipeline, and data and command inputs of the first stage being coupled to said central controller, and wherein said first means is adapted to alter a signal level on said data and command control lines to differentiate between the types of information on the bus.

Claim 4

The system of claim 2 wherein each stage further comprises: state decoder means for decoding command data on the bus, operative to provide internal control signals to stage components for executing the command, said state decoder means further providing a current state signal indicative of an operational state of the stage; and feedback means for feeding said current state signal back to an input of the decoder to provide logical decision information to determine the stage response to subsequent commands.

Claim 5

The system of claim 3 wherein said state decoder is further operative to control the state of the command output control line of the stage whereby subsequent commands are selectively passed on to succeeding stages in the pipeline depending upon the current state of the stage and the type of command received.

Claim 6

The system of claim 4 wherein each stage includes a bypass switch means coupled between the input and output lines of the bus for the stage; and neighborhood transformation control logic means in the processor portion, operative for transforming pixel data on the bus input lines and coupling the transformed pixel data to the next stage through the output bus lines.

Claim 7

The system of claim 5 wherein said decoder means is adapted to control said bypass switch means whereby pixel data on the bus may pass through the stage unaltered by the neighborhood transformation logic circuitry.

Claim 8

The system of claim 6 wherein said current state signal contains a plurality of bits, a group of which generally corresponds to the command currently being executed by the stage.

Claim 9

The system of claim 7 which further comprises: command detector means having inputs coupled to said bus input lines and to the group of bits containing the current command of the stage, an output coupled to a state decoder input, and a select input coupled to said command input line, said command detector means selectively coupling either the current command or a new command via said bus to the decoder input according to the state of the command input line.

Claim 10

The system of claim 8 wherein said data input lne is also coupled to an input of said state decoder.

Claim 11

The system of claim 1 wherein said memory portion includes a plurality of segments, at least one segment for storing transformation control instructions for the stage and another segment for storing pixel values to be transformed by the processor portion.

Claim 12

The system of claim 10 including means for loading said transformation control instructions into said one memory segment upon receipt of a given command; and means for loading pixel data into said other memory segment upon receipt of a different command.

Claim 13

The system of claim 11 including means for loading internal registers in the processor portion of the stage with selected contents of said one memory segment upon receipt of a particular command.

Claim 16

The method of claim 13 which further comprises: providing internal control signals to stage components for executing a command and generating current state indicia indicative of the resulting operational state of the stage; and utilizing said current state indicia to determine stage response to subsequent commands.

Claim 17

The method of claim 13 wherein each stage includes a memory portion and a processor portion for transforming image data according to transformation control instructions; and wherein said method further comprises: loading the memory portion of selected stages with transformation control instructions pursuant to a series of local commands.

Claim 18

The method of claim 15 further comprising the step of programming the first stage in the pipeline and then placing said first stage into a particular state which ignores subsequent commands for programming subsequent stages in the pipeline.

Claim 19

The method of claim 16 which further comprises the step of transferring selected transformation control instructions from the memory portions to the processor portions of the stages prior to processing image data whereby to prepare each stage for performing preselected transformations.

Claim 20

The method of claim 13 which further comprises: passing the data on the bus unaltered to the next stage in the pipeline in response to a particular command.

Claim 21

An image analyzer system comprising: a plurality of substantially identical neighborhood transformation stages that are serially connected in a pipeline, each stage having processor means for analyzing image data pursuant to programmable transformation control instructions; controller means for providing said transformation control instructions to the stages; communication link means having a first portion coupled between the controller and an input of only the first stage in the pipeline, operative to transfer both image data and control instructions for all of the stages in the pipeline; said communication link means having a second portion coupled between an output of the first stage and an input of a successive stage in the pipeline; operative to transfer both image data and control instructions for programming successive stages in the pipeline; and means for indicating whether image data or control instructions is being transferred over the communication link, whereby said stages are programmed by transferring control instructions over the communication link through preceeding stages in the pipeline, with image data being subsequently transferred over the same communication link through the pipeline for analysis by the programmed stages.

Claim 22

An image analyzer system comprising: a plurality of substantially identical neighborhood transformation stages that are serially connected in a pipeline, each stage having processor means for analyzing image data pursuant to programmable transformation control instructions; controller means for providing said transformation control instructions to the stages; communication link means having a first portion coupled between the controller and an input of only the first stage in the pipeline, operative to transfer both image data and control instructions for all of the stages in the pipeline; said communication link means having a second portion coupled between an output of the first stage and an input of a successive stage in the pipeline; operative to transfer both image data and control instructions for programming successive stages in the pipeline; and means for indicating whether image data or control instructions is being transferred over the communication link, whereby said stages are programmed by transferring control instructions over the communication link through preceeding stages in the pipeline, with image data being subsequently transferred over the same communication link through the pipeline for analysis by the programmed stages.