Data processing cells and parallel data processors incorporating such cells

Claim 2

A parallel data processor having a plurality of cells for processing digital data signals, the processor being characterised by: a controller (12; 12') for generating control signals in response to program instructions; and, a plurality of identical interconnected cells (P) each including an arithmetic processing element (20; 40) including three input terminals (Dl, D2, C) and two arithmetic output terminals, and a plurality of memories connected to the arithmetic processing element (20; 40) and the controller (12; 12'), the memories each being individually controllable to supply selected ones of a plurality of predetermined data signals to the input terminals of the arithmetic processing element in response to control signals from the controller, and the memories being connected to the arithmetic processing element and the controller such that both logical and arithmetic operations are performed by the arithmetic processing element.

Claim 3

A data processor according to claim 1, including n times m cells (P) interconnected in an n by m matrix with each cell connected to at least two neighboring cells or to at least one neighboring cell and an outside data source or sink.

Claim 4

A data processor according to claim 1, including n times m cells (P) interconnected in an n by m matrix with interior cells and edge cells, each interior cell of the matrix being connected to four neighboring cells and each edge cell of the matrix being connected to at least two neighboring cells and to a data input/output means (10) for supplying data to some of the edge cells and receiving data from some of the edge cells:

Claim 5

A data processor according to claim 1, claim 2 or claim 3, wherein the arithmetic processing element is a full adder (20; 40) having two data input terminals (Dl, D2), a carry input terminal (C), a sum output terminal and a carry output terminal.

Claim 6

A data processor according to claim 1, claim 2 or claim 3, wherein the arithmetic processing element is a full adder/subtractor (40) having two data input terminals (Dl, D2), a carry input terminal (C), a sum output terminal (+), a borrow output terminal (BW) and a carry output terminal (CY).

Claim 7

A data processor according to claim 4 or claim 5, wherein the plurality of memories includes a multi-bit memory (36; 60) having an output terminal and selectively addressable storage locations, the control signals from the controller (12; 12') including memory address signals (a0 - a ) for selectively applying stored data signals to the output terminal of the multi-bit memory.

Claim 8

A data processor according to claim 6, wherein the plurality of memories includes first, second and third single-bit data registers (22, 24, 26; 42, 44, 46), each selectively controllable to load one of the plurality of predetermined data signals.

Claim 9

A data processor according to claim 6 or claim 7, wherein the multi-bit memory (36; 60) is a random access memory.

Claim 10

A data processing cell for processing single bits of digital data, the cell being characterised by: a full adder (20) having first and second data input terminals (Dl, D2), a carry input terminal (C), a sum output terminal and a carry output terminal; an addressable, multi-bit memory (36) having a data input terminal, a data output terminal and a plurality of address terminals; bus selector means (34) for selectively applying an output signal from the output terminal of the multi-bit memory (36) or an output signal from the sum output terminal of the full adder (20) to a data bus in response to a first control signal; means (38) for selectively applying the output signal from the multi-bit memory (36) or a bus output signal from the data bus to the input terminal of the multi-bit memory in response to a second control signal; a carry input accumulator (32) for selectively applying a carry output signal from the carry output terminal or a desired logic level to the carry input terminal of the full adder (20) in response to a third control signal; a first data input accumulator means (28) for selectively applying a first data input signal, second data input signal or a bus input signal from the data bus to one of the first and second data input terminals of the full adder (20) in response to a fourth control signal; and, a second data input accumulator means (30) for selectively applying a third data input signal, a fourth data input signal or the bus input signal to the other of the first and second data input terminals of the full adder (20) in response to a fifth control signal.

Claim 11

A data processing cell for processing single bits of digital data, the cell being characterised by: a full adder (20) having first and second data input terminals (Dl, D2), a carry input terminal (C), a sum output terminal and a carry output terminal; an addressable, multi-bit memory (36) having a data input terminal, a data output terminal and a plurality of address terminals; bus selector means (34) for selectively applying an output signal from the output terminal of the multi-bit memory (36) or an output signal from the sum output terminal of the full adder (20) to a data bus in response to a first control signal; means (38) for selectively applying the output signal from the multi-bit memory (36) or a bus output signal from the data bus to the input terminal of the multi-bit memory in response to a second control signal; a carry input accumulator (32) for selectively applying a carry output signal from the carry output terminal or a desired logic level to the carry input terminal of the full adder (20) in response to a third control signal; a first data input accumulator means (28) for selectively applying a first data input signal, second data input signal or a bus input signal from the data bus to one of the first and second data input terminals of the full adder (20) in response to a fourth control signal; and, a second data input accumulator means (30) for selectively applying a third data input signal, a fourth data input signal or the bus input signal to the other of the first and second data input terminals of the full adder (20) in response to a fifth control signal.

Claim 12

A data processing cell for processing digital data signals, the cell being characterised by: a full, one bit adder (20; 40) having first and second data input terminals (D1, D2), a carry input terminal (C), a sum output terminal and a carry output terminal; a single bit carry memory (26; 46) connected to the carry input terminal (C) of the adder (20; 40); a first single bit data memory (22; 42) connected to one of the first and second data input terminals of the adder (20; 40); a second single bit data memory (24; 44) connected to the other of the first and second data input terminals of the adder (20; 40); a random access memory (36; 60) having data input and data output terminals; a data bus; bus selector means (34; 54) for selectively applying one of a plurality of single bit data signals; including at least the output signal from the random access memory output terminal and the output signal from the adder sum output terminal, to the data bus in response to a first control signal; means (32; 52) for selectively applying one of a plurality of single bit data signals, including the output signal from the adder carry output terminal and the signal stored by the single bit carry memory, to the single bit carry memory (26; 46) in response to a second control signal; means (28; 48) for selectively applying one of a plurality of single bit data signals, including the signal stored by the first single bit data memory (22; 42), the signal on the data bus and the output signals from two cell input terminals, to the first single bit data memory (22; 42) in response to a third control signal; and means (30; 50) for selectively applying one of a plurality of single bit data signals, including the signal stored by the second single bit data memory (24; 44), the signal on the data bus and the output signals from two cell input terminals, to the second single bit data memory (24; 44) in response to a fourth control signal.

Claim 13

A data processing cell for processing digital data signals, the cell being characterised by: a full, one bit adder (20; 40) having first and second data input terminals (D1, D2), a carry input terminal (C), a sum output terminal and a carry output terminal; a single bit carry memory (26; 46) connected to the carry input terminal (C) of the adder (20; 40); a first single bit data memory (22; 42) connected to one of the first and second data input terminals of the adder (20; 40); a second single bit data memory (24; 44) connected to the other of the first and second data input terminals of the adder (20; 40); a random access memory (36; 60) having data input and data output terminals; a data bus; bus selector means (34; 54) for selectively applying one of a plurality of single bit data signals; including at least the output signal from the random access memory output terminal and the output signal from the adder sum output terminal, to the data bus in response to a first control signal; means (32; 52) for selectively applying one of a plurality of single bit data signals, including the output signal from the adder carry output terminal and the signal stored by the single bit carry memory, to the single bit carry memory (26; 46) in response to a second control signal; means (28; 48) for selectively applying one of a plurality of single bit data signals, including the signal stored by the first single bit data memory (22; 42), the signal on the data bus and the output signals from two cell input terminals, to the first single bit data memory (22; 42) in response to a third control signal; and means (30; 50) for selectively applying one of a plurality of single bit data signals, including the signal stored by the second single bit data memory (24; 44), the signal on the data bus and the output signals from two cell input terminals, to the second single bit data memory (24; 44) in response to a fourth control signal.

Claim 14

A data processing cell for processing single bit, digital signals, the cell being characterised by: arithmetic processing means (20; 40) having first, second and third input terminals and at least first and second output terminals, the arithmetic processing means producing signals at the output terminals related to the arithmetic result of first, second and third input signals applied to the first, second and third input terminals, respectively; a plurality of single bit, digital signal memories connected to the first, second and third input terminals of the arithmetic processing means (20; 40) each for selectively storing one of a plurality of single bit data input signals as said first, second and, third input signals, respectively, in response to a control signal; and, an addressable, multi-bit memory (36; 60) having an output terminal providing, from an addressed memory location, one of the plurality of single bit data input signals; the arithmetic processing means (20; 40) and the memories being interconnected and controlled by said control signal so that the arithmetic processing means performs both arithmetic and logical operations with said plurality of single bit data input signals.

Claim 15

A data processing cell for processing single bit, digital signals, the cell being characterised by: arithmetic processing means (20; 40) having first, second and third input terminals and at least first and second output terminals, the arithmetic processing means producing signals at the output terminals related to the arithmetic result of first, second and third input signals applied to the first, second and third input terminals, respectively; a plurality of single bit, digital signal memories connected to the first, second and third input terminals of the arithmetic processing means (20; 40) each for selectively storing one of a plurality of single bit data input signals as said first, second and, third input signals, respectively, in response to a control signal; and, an addressable, multi-bit memory (36; 60) having an output terminal providing, from an addressed memory location, one of the plurality of single bit data input signals; the arithmetic processing means (20; 40) and the memories being interconnected and controlled by said control signal so that the arithmetic processing means performs both arithmetic and logical operations with said plurality of single bit data input signals.

Claim 16

A data processing cell according to claim 11, wherein the arithmetic processing means comprises a full adder (20; 40) having first and second data input terminals (Dl, D2), a carry input terminal (C), a sum output terminal and a carry output terminal.

Claim 17

A data processing cell according to claim 11, wherein the arithmetic processing element is a full adder/subtractor (40) having two data input terminals (Dl; D2), a carry input terminal (C), a sum output terminal (+), a borrow output terminal (BW) and a carry output terminal (CY).

Claim 18

A data processing cell according to claim 11, claim 12 or claim 13, wherein the multi-bit memory (36; 60) comprises selectively addressable storage locations and is responsive to memory address signals for selectively applying stored data signals to its output terminal.

Claim 19

A data processing cell according to any one of claims 11 to 14, wherein the plurality of single bit, digital signal memories includes first, second and third single-bit data registers (22, 24, 26; 42, 44, 46), each selectively controllable to load one of the plurality of single bit data input signals.

Claim 20

A data processing cell according to any one of claims 12 to 15, which includes a data bus and means for selectively applying one of a plurality of data signals including at least the signals, from the sum output terminals of the adder (20; 40) and the output terminal of the multi-bit memory (36; 60).

Claim 21

A data processing cell according to any one of claims 11 to 16, ' wherein the multi-bit memory (36; 60) is a random access memory.