SIMD array processor with global instruction control and reprogrammable instruction decoders

Claim 2

A SIMD array processor comprising: a multidimensional array of processing elements, each said processing element including decoding means for individually decoding a global instruction for local execution in said processing element; control logic for issuing said global instruction to said array of processing elements; an instruction bus connecting said control logic to each of said processing elements such that said global instructions are received in parallel by each said processing element, said instruction bus comprising a plurality of bus lines; said decoding means of at least one of said processing elements comprising; programmable modifying means connected to selected bus lines for locally modifying selected bits of said global instruction and outputting locally modified bits onto local bit lines; and fixed decoding means connected to said local bit lines for receiving said locally modified bits from said programmable modifying means, said fixed decoding means further connected to said bus lines for receiving unmodified bits of said global instruction; storage for receiving control information and/or data, each said processing element being associated with and having access to a respective block of said storage, said programmable modifying means of each said processing element being connected to said respective block of storage for receiving said control data for individually programming each said programmable modifying means; means for said control logic to access said storage and store control data for each said programmable modifying means in said respective blocks of storage; said fixed decoding means of each said processing element being simultaneously responsive to unmodified bits of a global load instruction on said instruction bus to cause said control data to be loaded from said respective blocks of storage into said programmable modifying means, irrespective of the value of said locally modified bits.

Claim 3

A SIMD array processor as claimed in claim 1 wherein said programmable modifying means comprises a look-up table.

Claim 4

A SIMD array processor as claimed in claim 2 wherein said look-up table comprises: a serial write port connected to said block of storage for receiving modification serially therefrom; and a parallel write port connected to said selected bus lines for receiving said selected bits of said global instruction in parallel.

Claim 5

A SIMD array processor as in claim 1 wherein said programmable modifying means is connected to said selected bus lines for receiving bits of a global shift instruction which determine a shift direction, said programmable modifying means being responsive to said global shift instruction so as to locally modify said global shift instruction such that data may be distributed throughout the array at any one time in a plurality of directions within the array.

Claim 6

A SIMD array processor as claimed in claim 4 wherein said processing elements of said array are interconnected in two orthogonal directions, each processing element in said array having an input multiplexer, a first output register which is connected to the input multiplexer of two logically adjacent said processing elements in a first said orthogonal direction and a second output register which is connected to the input multiplexer of two logically adjacent said processing elements in a second said orthogonal direction whereby multiple simultaneous data shift operations may be performed in a plurality of directions at one time within a said processing element.

Claim 7

A display system comprising: a host processor including a display device; and a SIMD array processor comprising: a multidimensional array of processing elements, each said processing element including decoding means for individually decoding a global instruction for local execution in that processing element; control logic for issuing said global instruction to said array of processing elements; an instruction bus connecting said control logic to each of said processing elements such that said global instructions are received in parallel by each said processing element, said instruction bus comprising a plurality of bus lines; said decoding means of at least one of said processing elements comprising: programmable modifying means connected to selected bus lines for locally modifying selected bits of said global instruction and outputting locally modified bits onto local bit lines; and fixed decoding means connected to said local bit lines for receiving said locally modified bits from said programmable modifying means, said fixed decoding means further connected to said bus lines for receiving unmodified bits of said global instruction; storage for receiving control information and/or data, each said processing element being associated with and having access to a respective block of said storage, said programmable modifying means of each said processing element being connected to said respective block of storage for receiving said control data for individually programming each said programmable modifying means; means for said control logic to access said storage and store control data for each said programmable modifying means in said respective blocks of storage; said fixed decoding means of each said processing element being simultaneously responsive to unmodified bits of a global load instruction on said instruction bus to cause said control data to be loaded from said respective blocks of storage into said programmable modifying means, irrespective of the value of said locally modified bits.

Claim 8

A display system comprising: a host processor including a display device; and a SIMD array processor comprising: a multidimensional array of processing elements, each said processing element including decoding means for individually decoding a global instruction for local execution in that processing element; control logic for issuing said global instruction to said array of processing elements; an instruction bus connecting said control logic to each of said processing elements such that said global instructions are received in parallel by each said processing element, said instruction bus comprising a plurality of bus lines; said decoding means of at least one of said processing elements comprising: programmable modifying means connected to selected bus lines for locally modifying selected bits of said global instruction and outputting locally modified bits onto local bit lines; and fixed decoding means connected to said local bit lines for receiving said locally modified bits from said programmable modifying means, said fixed decoding means further connected to said bus lines for receiving unmodified bits of said global instruction; storage for receiving control information and/or data, each said processing element being associated with and having access to a respective block of said storage, said programmable modifying means of each said processing element being connected to said respective block of storage for receiving said control data for individually programming each said programmable modifying means; means for said control logic to access said storage and store control data for each said programmable modifying means in said respective blocks of storage; said fixed decoding means of each said processing element being simultaneously responsive to unmodified bits of a global load instruction on said instruction bus to cause said control data to be loaded from said respective blocks of storage into said programmable modifying means, irrespective of the value of said locally modified bits.

Claim 9

A display system as recited in claim 6 wherein said programmable modifying means of said SIMD array processor comprises a look-up table.

Claim 10

A display system as recited in claim 7 wherein said look-up table comprises a serial write port connected to said block of storage for receiving modification serially therefrom and a parallel write port connected to said selected bus lines for receiving said selected bits of said global instruction in parallel.

Claim 11

A display system as recited in claim 6 in which the programmable modifying means of said SIMD array processor is connected to said selected bus lines for receiving bits of a global shift instruction which determine a shift direction, whereby the programmable modifying means may be programmed to locally modify a global shift instruction such that data may be distributed throughout the array at any one time in a plurality of directions within the array.

Claim 12

A display system as claimed in claim 9 wherein said processing elements of said array are interconnected in two orthogonal directions, each processing element in the array comprising an input multiplexer, a first output register which is connected to the input multiplexer of two logically adjacent said processing elements in a first said orthogonal direction and a second output register which is connected to the input multiplexer of two logically adjacent said processing elements in a second said orthogonal direction whereby multiple simultaneous data shift operations may be performed in a plurality of directions at one time within a said processing element.