Processor array with means to control cell processing state

Claim 2

A processor array of the type including a plurality of processor cells typically arranged in a matrix having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array and associated with a program memory for storage of data and instructions, with said controller typically further coupled to an address generator for accessing of the cells in said array, characterized in this that, for causing each cell in- said array to manifest an operative state or an idle state according to data and instructions processed by said cell,it further includes : arithmetic logic means (30,31) having a plurality of input ports for receiving data from said controller and an output port, logic means including a control register(40) coupled to said output port and operative to receive a predetermined instruction from said controller indicative of a given bit state manifesting said operative condition, whereby if said given bit state is not detected, said cell is rendered idle, and means included in said logic means operative to detect said given bit state indicative of said operative state for said cell.

Claim 3

The processor array according to claim 1, wherein said processor array is arranged as a single instruction multiple data array.

Claim 4

The processor array according to claim 1, wherein said arithmetic logic means includes a multiport RAM (30) having multiple input ports each port adapted to receive control signals from said controller(21)to enable data to be read or written into said RAM, said RAM having a plurality of outputs coupled to associated inputs of an arithmetic logic unit (ALU)( 31 )with an input of said ALU coupled to said logic means.

Claim 5

The processor array according to claim 3, further including a status register(34) coupled to said output of said ALU (21) and capable of storing therein the results of a computation performed by said cell when said cell is in said operative state.

Claim 6

The processor array according to claim 4, wherein said logic means further includes a programmable logic array (42) for decoding the states of said status register, the selected state being chosen by the controller (21) with a output coupled to said control register (40).

Claim 7

The processor array according to claim 5, wherein said control register(40)has a first input designated as a POP input and coupled to said controller for causing said register to shift to the right a received binary one into said control register, and further having a second input designated as a PUSH input to enable said control register to shift data to the left for receiving a test condition bit.

Claim 8

The processor array according to claim 6, wherein said control register (40) is a clocked shift left, shift right, parallel in/parallel out shift register operative to shift to the right for a true on said POP input and operative to shift to the left for a true on said PUSH input.

Claim 9

The processor array according to claim 7, wherein said control register (40) further has a third input designated as a left serial input for receiving data from said controller (21) for shifting to the left and a fourth input designated as a right serial input for receiving data from said controller (21) for shifting to the right.

Claim 10

The processor array according to claim 8, wherein said control register (40) further includes a parallel input designated as LOAD for restoring the state of said register as controlled by said controller (21).

Claim 11

The processor array according to claim 9, wherein said controller (21) further includes means for counting the number of bits PUSHED into said control register to determine whether said number of bits are capable of being accommodated by said register.

Claim 12

The processor array according to claim 1, wherein said array memory has stored therein a plurality of masks indicative of the square of the number of processing cells in said array, with said controller(21) operative to select any desired one of said masks by transmitting an address to said address generator (24) indicative of each of said cells for storing therein data indicative of said mask as selected.

Claim 13

The processor array according to claim 11, wherein said masks include a first plurality of masks indicative of vertical columns M in said array and a second plurality of masks indicative of horizontal rows N in said array.

Claim 14

The processor array according to claim 12, wherein said program control memory (22) comprises a plurality of random access memories (RAMS), with said controller(21) being a programmed sequencer.

Claim 15

A processor array of the type including a plurality of individual processing cells arranged in a N x M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, characterized in this that the structure of a processing cell structure included in said array comprises : memory means (30) having multiple input ports each for receiving separate input data from said controller(21) and a plurality of output ports, an arithmetic logic unit (ALU) (31) having a plurality of input ports each separate one coupled to an associated output port of said memory means, with said arithmetic logic unit having an output port, first registermeans (34) coupled to said output port of said ALU for determining the status of said cell, second register means(34) coupled to said first register means and said controller and operative to receive data and instruction from said controller (21) and said first register means (34) to store therein a first code indicative of an operating condition for said cell and a second code indicative of an idle condition for said cell whereby said cell has the ability to operate or remain idle depending upon said data instructions received.

Claim 16

A processor array of the type including a plurality of individual processing cells arranged in a N x M matrix, having M columns and N rows, with said processing cells each connected to neighboring cells in the vertical and horizontal directions to form said array, with said array being coupled to a controller for providing instructions to said array with said controller coupled to a program memory for storage of data and instructions, with said controller being further coupled to inputs of an address generator having outputs coupled to said array for accessing groups of cells in said array, characterized in this that the structure of a processing cell structure included in said array comprises : memory means (30) having multiple input ports each for receiving separate input data from said controller(21) and a plurality of output ports, an arithmetic logic unit (ALU) (31) having a plurality of input ports each separate one coupled to an associated output port of said memory means, with said arithmetic logic unit having an output port, first registermeans (34) coupled to said output port of said ALU for determining the status of said cell, second register means(34) coupled to said first register means and said controller and operative to receive data and instruction from said controller (21) and said first register means (34) to store therein a first code indicative of an operating condition for said cell and a second code indicative of an idle condition for said cell whereby said cell has the ability to operate or remain idle depending upon said data instructions received.

Claim 17

The processor array according to claim 14, wherein said memory means (30) isaRAM having a read address input, a read/write address input, with at least two outputs.

Claim 18

The processor array according to claim 15, wherein said outputs of said RAM (30) are respectively coupled to an associated input of said ALU (31).

Claim 19

The processor array according to claim 14, wherein said first register means (34) includes a status register (34) for storing therein the result of an arithmetic operation implemented by said ALU (31) such as carry, negative, zero and overflow.

Claim 20

The processor array according to claim 14, wherein said second register means (40) is a control register (40) having a first input designated as a POP input for shifting to the right a received binary one, and a second input designated as a PUSH input for shifting to the left a test condition result.

Claim 21

The processor array according to claim 18, Wherein said control register(40)is a clocked shift left, shift right, parallel in/parallel out shift register operative to shift to the right for a high on said POP input and operative to shift to the left for a high on said PUSH input.

Claim 22

The processor array according to claim 19, wherein said control register (40) further has a third input designated as a left serial input for receiving data from said controller for shifting to the left and a fourth input designated as a right serial input for receiving data from said controller for shifting to the right.