Method for manufacturing a stimulus wafer for use in a wafer-to-wafer testing system to test integrated circuits located on a product wafer

Claim 1

A method for forming a stimulus wafer, the stimulus wafer being formed for stimulating a semiconductor product wafer, the method for forming the stimulus wafer comprising: providing a substrate having a surface; forming, on the surface of the substrate in a first area, a plurality of input/output terminals coupled so that the input/output terminals provide test control signals external to the stimulus wafer; forming, on the surface of the substrate in a second area different from the first area, a plurality of integrated circuits wherein each integrated circuit in the plurality of integrated circuits contains test circuits coupled to top level conductive pads, the top level conductive pads being configured to allow the test circuits in the plurality of the integrated circuits to test product integrated circuits on the semiconductor product wafer via electrical test signals originating in the test circuits and transmitted through the top level conductive pads, the plurality of integrated circuits being laid out in a predetermined two-dimensional geometry across the surface of the substrate, the test circuits comprising circuitry for controlling voltage to the semiconductor product wafer, circuitry for controlling current to the semiconductor product wafer, and circuitry for controlling signals through the top level conductive pads to the semiconductor product wafer; forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising temperature monitoring circuitry and performance monitoring circuitry for identifying which circuits in the plurality of driver circuits have identified a stimulus problem on the semiconductor product wafer; forming a stimulus wafer conductive interconnect network for coupling signals between the plurality of input/output terminals, the plurality of driver circuits, and the at least one feedback circuit.

Claim 2

A method for forming a stimulus wafer, the stimulus wafer being formed for stimulating a semiconductor product wafer, the method for forming the stimulus wafer comprising: providing a substrate having a surface; forming, on the surface of the substrate in a first area, a plurality of input/output terminals coupled so that the input/output terminals provide test control signals external to the stimulus wafer; forming, on the surface of the substrate in a second area different from the first area, a plurality of integrated circuits wherein each integrated circuit in the plurality of integrated circuits contains test circuits coupled to top level conductive pads, the top level conductive pads being configured to allow the test circuits in the plurality of the integrated circuits to test product integrated circuits on the semiconductor product wafer via electrical test signals originating in the test circuits and transmitted through the top level conductive pads, the plurality of integrated circuits being laid out in a predetermined two-dimensional geometry across the surface of the substrate, the test circuits comprising circuitry for controlling voltage to the semiconductor product wafer, circuitry for controlling current to the semiconductor product wafer, and circuitry for controlling signals through the top level conductive pads to the semiconductor product wafer; forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising temperature monitoring circuitry and performance monitoring circuitry for identifying which circuits in the plurality of driver circuits have identified a stimulus problem on the semiconductor product wafer; forming a stimulus wafer conductive interconnect network for coupling signals between the plurality of input/output terminals, the plurality of driver circuits, and the at least one feedback circuit.

Claim 9

A method for forming a stimulus wafer, the stimulus wafer being formed for testing a semiconductor product wafer, the method for forming the stimulus wafer comprising: providing a substrate having a surface; patterning, on the surface of the substrate in a first area, a plurality of input/output terminals for communication of information external to the stimulus wafer; coupling conductive wire to the plurality of input/output terminals for communication of the information external to the stimulus wafer, the conductive wire being coupled to the input/output terminals by a physical bonding technique; forming, on the surface of the substrate in a second area different from the first area, a plurality of test circuits, the plurality of test circuits comprising circuitry for providing voltage, circuitry for monitoring current, and circuitry for driving test signals through upper level bond pads to enable testing of product circuits on another wafer, the test circuits being spatially configured into a two-dimensional layout of integrated circuits across the stimulus wafer where scribe lines separate the integrated circuits; forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising circuitry for identifying which test circuits in the plurality of test circuits have identified a test problem in at least one product circuit on another wafer; forming a stimulus wafer conductive interconnect network for coupling signals between at least two of the plurality of input/output terminals, the plurality of test circuits, and the at least one feedback circuit; and forming an interconnect media overlying the plurality of test circuits wherein the interconnect media comprising an insulating portion and a plurality of conductive fibers through the insulating portion wherein the insulating portion separates each conductive fiber from all other conductive fibers, the plurality of conductive fibers being coupled to the circuitry for driving test signals within the plurality of test circuits for communicating the test signals to the products circuits of another wafer via the plurality of conductive fibers.

Claim 10

A method for forming a stimulus wafer, the stimulus wafer being formed for testing a semiconductor product wafer, the method for forming the stimulus wafer comprising: providing a substrate having a surface; patterning, on the surface of the substrate in a first area, a plurality of input/output terminals for communication of information external to the stimulus wafer; coupling conductive wire to the plurality of input/output terminals for communication of the information external to the stimulus wafer, the conductive wire being coupled to the input/output terminals by a physical bonding technique; forming, on the surface of the substrate in a second area different from the first area, a plurality of test circuits, the plurality of test circuits comprising circuitry for providing voltage, circuitry for monitoring current, and circuitry for driving test signals through upper level bond pads to enable testing of product circuits on another wafer, the test circuits being spatially configured into a two-dimensional layout of integrated circuits across the stimulus wafer where scribe lines separate the integrated circuits; forming at least one feedback circuit, on the surface of the substrate in a third area which is different from both the first and second area, the at least one feedback circuit comprising circuitry for identifying which test circuits in the plurality of test circuits have identified a test problem in at least one product circuit on another wafer; forming a stimulus wafer conductive interconnect network for coupling signals between at least two of the plurality of input/output terminals, the plurality of test circuits, and the at least one feedback circuit; and forming an interconnect media overlying the plurality of test circuits wherein the interconnect media comprising an insulating portion and a plurality of conductive fibers through the insulating portion wherein the insulating portion separates each conductive fiber from all other conductive fibers, the plurality of conductive fibers being coupled to the circuitry for driving test signals within the plurality of test circuits for communicating the test signals to the products circuits of another wafer via the plurality of conductive fibers.

Claim 17

A method for forming a stimulus wafer for testing product integrated circuits on a product wafer, the method comprising the steps of: providing the stimulus wafer as a semiconductor wafer; depositing a plurality of conductive layers and a plurality of dielectric layers on the stimulus wafer to form: (1) a plurality of test integrated circuit die separated from each other by scribe lines and used for generating test signals to test another semiconductor wafer; (2) at least one contact area coupled to at least one test integrated circuit die for communicating information to and from the at least one test integrated circuit die to an external tester to enable testing of another semiconductor wafer; and (3) at least one feedback circuit wherein the at least one feedback circuit is coupled to the at least one contact area for communicating temperature information to the external tester, the plurality of test integrated circuit die having a top conductive layer of metal; and forming a compliant interconnect media coupled to the top conductive layer of metal, the compliant interconnect media comprising dielectric material surrounding a plurality of conductive fibers wherein the conductive fibers couple to the top conductive layer of metal and provide electrical signals to test the integrated circuits on the product wafer.

Claim 18

A method for forming a stimulus wafer for testing product integrated circuits on a product wafer, the method comprising the steps of: providing the stimulus wafer as a semiconductor wafer; depositing a plurality of conductive layers and a plurality of dielectric layers on the stimulus wafer to form: (1) a plurality of test integrated circuit die separated from each other by scribe lines and used for generating test signals to test another semiconductor wafer; (2) at least one contact area coupled to at least one test integrated circuit die for communicating information to and from the at least one test integrated circuit die to an external tester to enable testing of another semiconductor wafer; and (3) at least one feedback circuit wherein the at least one feedback circuit is coupled to the at least one contact area for communicating temperature information to the external tester, the plurality of test integrated circuit die having a top conductive layer of metal; and forming a compliant interconnect media coupled to the top conductive layer of metal, the compliant interconnect media comprising dielectric material surrounding a plurality of conductive fibers wherein the conductive fibers couple to the top conductive layer of metal and provide electrical signals to test the integrated circuits on the product wafer.