US5279975A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of testing individual dies on semiconductor wafers prior to singulation
Assignee: Micron Technology Inc
•
Filing: 1992-02-07
•
Granted: 1994-01-18
•
Expires: 2012-02-07
Abstract
Abstract A method of processing and testing a semiconductor wafer containing an array of integrated circuit dies comprises: a) providing die test cycling circuitry on the wafer b) etching contact openings through a passivation layer atop the wafer to Vcc and Vss pads associated with individual dies; c) patterning a layer of conductive material atop the water to provide a Vcc bus and a Vss bus which interconnect with the Vcc and Vss pads respectively, the Vcc bus electrically connecting with the test cycling circuitry; d) burn-in testing the wafer with selected voltages being applied to the Vss and Vcc buses e) etching the Vcc bus and Vss bus from the wafer; f) etching contact openings through the passivation layer to conductive pads on individual dies; g) testing the individual dies for operability by engaging the conductive pads with testing equipment; h) identifying operable dies; i) singulating the dies; and j) collecting the operable dies.
Inventors
- 👤 Kevin M. Devereaux
- 👤 Mark Bunn
- 👤 Brian Higgins
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:33
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2884; G01R31/2886
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
239 words
A method of processing and of testing a semiconductor wafer containing an array of integrated circuit dies, the wafer including areas of individual die circuitry and areas of distinct scribe line area which are separate from the individual die circuitry areas, the method comprising the following steps: providing die test cycling circuitry on the wafer for test cycling individual dies; providing a passivation layer atop the wafer; etching contact openings through the passivation layer to Vcc and Vss pads associated with individual dies; providing a layer of conductive material atop the wafer; patterning the layer of conductive material to provide a Vcc bus and a Vss bus atop the dies which interconnect with the Vcc and Vss pads respectively, the Vcc and Vss busses each including respective straight-line bus portions extending fully between individual die circuitry areas, each straight-line portion overlying a plurality of the individual die circuitry areas, the Vcc bus electrically connecting with the test cycling circuitry; burn-in testing the wafer with voltages being applied to the Vss and Vcc buses to cycle the individual dies during burn-in testing; etching the Vcc bus and Vss bus from the wafer; etching contact openings through the passivation layer to conductive pads on individual dies; testing the individual dies on the wafer for operability by engaging the conductive pads with testing equipment; identifying operable and inoperable dies; severing through the wafer to singulate the dies; and collecting the operable dies.
Claim 2
Independent Claim
239 words
A method of processing and of testing a semiconductor wafer containing an array of integrated circuit dies, the wafer including areas of individual die circuitry and areas of distinct scribe line area which are separate from the individual die circuitry areas, the method comprising the following steps: providing die test cycling circuitry on the wafer for test cycling individual dies; providing a passivation layer atop the wafer; etching contact openings through the passivation layer to Vcc and Vss pads associated with individual dies; providing a layer of conductive material atop the wafer; patterning the layer of conductive material to provide a Vcc bus and a Vss bus atop the dies which interconnect with the Vcc and Vss pads respectively, the Vcc and Vss busses each including respective straight-line bus portions extending fully between individual die circuitry areas, each straight-line portion overlying a plurality of the individual die circuitry areas, the Vcc bus electrically connecting with the test cycling circuitry; burn-in testing the wafer with voltages being applied to the Vss and Vcc buses to cycle the individual dies during burn-in testing; etching the Vcc bus and Vss bus from the wafer; etching contact openings through the passivation layer to conductive pads on individual dies; testing the individual dies on the wafer for operability by engaging the conductive pads with testing equipment; identifying operable and inoperable dies; severing through the wafer to singulate the dies; and collecting the operable dies.
Claim 3
Dependent Claim
38 words
The method of processing and of testing a semiconductor wafer of claim 1 wherein the array includes scribe line area between and separating individual dies, and further comprising providing the test cycling circuitry in the scribe line area.
Claim 4
Dependent Claim
32 words
The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry associated with individual dies.
Claim 5
Dependent Claim
25 words
The method of processing and of testing a semiconductor wafer of claim 3 further comprising providing the individual test cycling circuitry on the individual dies.
Claim 6
Dependent Claim
39 words
The method of processing and of testing a semiconductor wafer of claim 3 wherein the array includes scribe line area between and separating individual dies, and further comprising providing the individual test cycling circuitry in the scribe line area.
Claim 7
Dependent Claim
69 words
The method of processing and of testing a semiconductor wafer of claim 1 further comprising utilizing the test cycling circuitry to: write data to the dies and read data from the dies; compare the data written to the dies with the data read from the dies; and provide an error indication if the data written to the dies is not the same as the data read from the dies.
Claim 8
Dependent Claim
77 words
The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrificial Vcc pads, the Vss bus connecting with the sacrificial Vss pads.
Claim 9
Dependent Claim
29 words
The method of processing and of testing a semiconductor wafer of claim 7 further comprising patterning the wafer to provide the sacrificial Vcc and Vss pads on individual dies.
Claim 10
Dependent Claim
132 words
The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies and being engaged by the Vcc bus; the method further comprising: patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual die sacrificial Vss pads.
Claim 11
Dependent Claim
30 words
The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the conductive layer to provide fuses between the Vcc bus and individual Vcc pads.
Claim 12
Dependent Claim
94 words
The method of processing and of testing a semiconductor wafer of claim 1 further comprising patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads associated with the dies, the respective permanent and sacrificial pads being connected relative to one another in parallel, the Vcc bus connecting with the sacrifical Vcc pads, the Vss bus connecting with the sacrificial Vss pads, the conductive layer being patterned to provide fuses between the Vcc bus and the sacrificial Vcc pads.
Claim 13
Dependent Claim
149 words
The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of providing die test cycling circuitry comprises providing individual test cycling circuitry on the individual dies, a cycling test pad being associated with the individual test cycling circuitry and being provided on the individual dies and being engaged by the Vcc bus; the method further comprising: patterning the wafer to provide permanent Vcc and permanent Vss pads on the individual dies, and patterning the wafer to provide sacrificial Vcc and Vss pads on the individual dies, the respective permanent and sacrificial pads being connected relative to one another in parallel on the individual dies, the Vcc bus connecting with the individual die sacrificial Vcc pads, the Vss bus connecting with the individual die sacrificial Vss pads, the conductive layer being patterned to provide fuses between the Vcc bus and the sacrificial Vcc pads.
Claim 14
Dependent Claim
40 words
The method of processing and of testing a semiconductor wafer of claim 1 wherein the step of etching the Vcc bus and Vss bus from the wafer is conducted without any prior photomaking of the Vcc buss and Vss bus.
References Cited (Backward Citations)
US3835530A
Cited
US3839781A
Cited
US3795972A
Cited
US3849872A
Cited
US4104785A
Cited
US4288911A
Cited
JPS57188159A
Cited
US4778771A
Cited
US4866714A
Cited
US4967146A
Cited
US5047711A
Cited
US5059899A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-01-17 | 1997-07-19 | 1998-01-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-01-17 | 2001-07-19 | 2002-01-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-01-17 | 2005-07-19 | 2006-01-18 | $7700.00 | Window Closed / Lapsed |