Integrated circuit interconnections by pad relocation

Claim 2

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on an integrated circuit wafer having a plurality of operable and inoperable circuits, the operable and inoperable circuits having random positions in a non-uniform distribution and having primary signal-connect means associated therewith at a level of wafer metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations defining the desired positions of operable circuits to be subjected to standardized masking processes utilizing standardized opening means and standardized masking means, the predetermined circuit locations corresponding to identical desired locations of good circuits of all wafers to be similarly processed into the electrical function; testing the plurality of operable and inoperable circuits at the primary signal-connect means to determine actual positions of operable and inoperable circuits; comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern and selecting operable circuits from any of the tested operable circuits irrespective of their position and distribution on the wafer, the number of the selected operable circuits being at least equal to the number of predetermined circuit locations on the master pattern; electrically routing each of the primary signal-connect means of each of the selected operable circuits to sites of secondary signal-connect means of each of the selected operable circuits, said sites being located within the desired positions corresponding to the predetermined circuit locations of the master pattern, whereby each of the selected operable circuits are terminated in the secondary signal-connect means and in the desired positions corresponding to the predetermined circuit locations of the master pattern; and further electrically coupling the wafer circuits from the secondary signal-connect means into the electrical function by use of the standardized masking means, with the standardized opening means therein conforming in position to the positions of said secondary signal-connect means and any further signalconnect means, in a manner identical to all of the wafers to be similarly processed by the standardized masking processes into the electrical function.

Claim 3

The method of claim 1 wherein said first coupling and routing step further comprises the steps of: electrically isolating each of the inoperable circuits, including each of the inoperable circuits coinciding with any ones of the predetermined circuit locations, and electrically isolating each of the unselected operable circuits by deposition of insulation material over the first level of metallization; exposing the primary signal-connect means of only the selected operable circuits by masking and insulation material removal means; and routing electrical conduction means from the exposed primary signal-connect means to the sites of the secondary signal-connect means, whereby some of the secondary signal-connect means at the predetermined circuit locations are situated over or near a corresponding number of the inoperable circuits in electrical isolation therefrom.

Claim 4

The method of claim 1 in which said first coupling and routing step includes the step of routing electrical conductors in line segments from the primary signal-connect means of the selected operable circuits to the sites of the secondary signal-connect means.

Claim 5

The method of claim 3 in which said routing step includes the steps of forming a layer of photoresIst material on all of the circuits and orthogonally moving the wafer relative to a beam of ultraviolet light in at least first axial and second axial directions.

Claim 6

The method of claim 1 in which said first coupling and routing step includes the step of routing electrical conductors in line segments including curved line segments from the primary signal-connect means of the selected operable circuits to the sites of the secondary signal-connect means.

Claim 7

The method of claim 1 for use with a plurality of the wafers, further including the steps of electrically coupling the primary signal-connect means of any ones of the selected operable circuits of each of the wafers to the sites of the secondary signal-connect means and electrically coupling in an indentical manner for each of the wafers the secondary signal-connect means thereof by use of the standardized masking processes utilizing the standardized masking means, with the standardized opening means therein conforming in position to the positions of said secondary signal-connect means and any further signal-connect means into identical circuit configurations corresponding to the electrical function.

Claim 8

The method of claim 1 wherein said first coupling and routing step comprises the steps of: forming a first layer of photoresist material over the operable and inoperable circuits and the wafer; exposing portions of the first photoresist layer overlaying the primary signal-connect means of the selected operable circuits through masking means to light to form exposed portions and unexposed portions of the first photoresist layer; removing the unexposed portions of the first photoresist layer; forming a layer of electrically insulating material over the circuits and the exposed photoresist portions of the first layer; heating the device to crack the insulating material over the first layer exposed photoresist portions; removing the first layer exposed photoresist portions and the cracked insulating material to expose the primary signal-connect means of the selected circuits through feed-through means in the insulating material; forming a layer of electrically conductive material on the insulating material and the exposed primary signal-connect means; forming a second layer of photoresist material on the layer of electrically conductive material; exposing portions of the second photoresist layer in a pattern of interconnect lines extending from the exposed primary signal-connect means of the selected circuits to the sites of the secondary signal-connect means to form exposed and unexposed portions of the second photoresist layer; removing the second layer unexposed photoresist portions to expose portions of the conductive material; removing the exposed portions of the conductive material; and removing the exposed photoresist portions, leaving the conductive material in the pattern of interconnect lines, extending from the primary signal-connect means of the selected operable circuits to the sites of the secondary signal-connect means.

Claim 9

The method of claim 7 in which said step of exposing the second layer of photoresist material in the pattern of interconnect lines further includes the step of focusing a beam of light on the second layer of photoresist; and moving the integrated circuit wafer relative to the beam of light in a first axial direction and in a second axial direction at right angles to the first axial direction to expose the second layer of photoresist in the pattern of interconnect lines.

Claim 10

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on each of a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the operable and inoperable circuits having primary signal-connect means associated therewith in a level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining desired identical positions of operable circuits to be subjected to identical processing utilizing identical masking means at a level subsequent to the level of metallization; testing the plurality of operative and inoperative circuits of each of the wafers at the primary signal-connect means to determine actual positions of operable and inoperable circuits; for each of the wafers, comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern and selecting operable circuits from any of the tested operable circuits irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable circuits at least capable of performing the electrical function, and the number of the selected operable circuits being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the circuits and over the primary signal-connect means, with feedthrough means in the insulation layer opening at least to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically routing each of the primary signal-connect means of each of the selected operable circuits through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable circuits said sites being located within the desired positions corresponding to the predetermined circuit locations of the master pattern, whereby each of the selected operable circuits are terminated in the secondary signal-connect means and in the desired identical positions corresponding to the predetermined circuit locations of the master pattern; and further identical processing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of the identical processing utilizing the identical masking means identical to all of the wafers for interconnecting the selected operable circuits thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 11

An integrated circuit interconnection method for interconnecting operable circuits into an electrical function on each of a plurality of integrated circuit wafers, each capable of performing the same electrical function, each of the wafers having a plurality of operable and inoperable circuits in random positions of a non-uniform distribution, each of the operable and inoperable circuits having primary signal-connect means associated therewith in a level of metallization, comprising the steps of: preparing a master pattern having predetermined circuit locations, for each and every one of the wafers, the master pattern defining desired identical positions of operable circuits to be subjected to identical processing utilizing identical masking means at a level subsequent to the level of metallization; testing the plurality of operative and inoperative circuits of each of the wafers at the primary signal-connect means to determine actual positions of operable and inoperable circuits; for each of the wafers, comparing the actual positions of the tested operable circuits to the desired positions as determined by the master pattern and selecting operable circuits from any of the tested operable circuits irrespective of the position and distribution thereof on individual ones of the wafers, the number of selected operable circuits at least capable of performing the electrical function, and the number of the selected operable circuits being at least equal to the number of predetermined circuit locations of the master pattern; for each of the wafers, electrically insulating the operable and inoperable circuits and the primary signal-connect means from one another to form a first insulation layer over the circuits and over the primary signal-connect means, with feedthrough means in the insulation layer opening at least to the primary signal-connect means of the selected operable circuits; for each of the wafers, electrically routing each of the primary signal-connect means of each of the selected operable circuits through the feedthrough means and to sites of secondary signal-connect means of each of the selected operable circuits said sites being located within the desired positions corresponding to the predetermined circuit locations of the master pattern, whereby each of the selected operable circuits are terminated in the secondary signal-connect means and in the desired identical positions corresponding to the predetermined circuit locations of the master pattern; and further identical processing of each of the plurality of wafers from the secondary signal-connect means of each of the wafers by use of the identical processing utilizing the identical masking means identical to all of the wafers for interconnecting the selected operable circuits thereof in such a manner as to enable each of the wafers to perform the electrical function.

Claim 12

A method as in claim 9 wherein said step of preparing the master pattern of the predetermined circuit locations comprises the step of placing the locations in accordance with the expected density of the selected operable circuits.