US5130644A
Expired / Lapsed
US
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Integrated circuit self-testing device and method
Assignee: Texas Instruments Inc
•
Filing: 1991-01-29
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Granted: 1992-07-14
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Expires: 2011-01-29
Abstract
Abstract A semiconductor wafer (26) may have all the integrated circuits (36) formed thereon simultaneously self-tested by the addition of a power circuit, a ground circuit and clock circuit. Lead lines are formed during metallization of the integrated circuits (36) on the wafer (26). The lead lines are interconnected to the integrated circuits (36) to form a power input, a ground input and a clock input on each integrated circuit (36). A test head (28) having a power probe (44), a ground probe (46) and clock probe (48) is attached to the power, ground and clock circuits on the semiconductor wafer (36). The integrated circuits (36) are simultaneously tested by the test head (28), and failed circuits are identified by an infrared detector (42).
Inventors
- 👤 Granville E. Ott
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 08:37
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/317; G01R31/3181; G01R31/3185; G01R31/318516; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/07342; G01R31/31727
Claims Analysis
Total Claims: 32
Claim 1
Independent Claim
98 words
A method for forming a semiconductor wafer for simultaneously self testing integrated circuits thereon, comprising the steps of: interconnecting a power circuit formed in a first metallization layer to a power input on the integrated circuits; interconnecting a ground circuit formed in said first metallization layer to a ground input on the integrated circuits; interconnecting a clock circuit formed in a second metallization layer to a clock input on the integrated circuits to allow the integrated circuits to be simultaneously tested; and interconnecting an infrared indicating circuit to optically indicate a test pass/fail condition for each integrated circuit.
Claim 2
Independent Claim
98 words
A method for forming a semiconductor wafer for simultaneously self testing integrated circuits thereon, comprising the steps of: interconnecting a power circuit formed in a first metallization layer to a power input on the integrated circuits; interconnecting a ground circuit formed in said first metallization layer to a ground input on the integrated circuits; interconnecting a clock circuit formed in a second metallization layer to a clock input on the integrated circuits to allow the integrated circuits to be simultaneously tested; and interconnecting an infrared indicating circuit to optically indicate a test pass/fail condition for each integrated circuit.
Claim 3
Dependent Claim
44 words
The method of claim 1, wherein the step of interconnecting said power circuit comprises the steps of: forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and connecting said lines to form a bus for power input.
Claim 4
Dependent Claim
44 words
The method of claim 1, wherein the step of interconnecting said ground circuit comprises the steps of: forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and connecting said lines to form a bus for ground input.
Claim 5
Dependent Claim
44 words
The method of claim 1, wherein the step of interconnecting said clock circuit comprises the steps of: forming a plurality of lead lines between the integrated circuits during a metallization of the wafer; and connecting said lines to form a bus for clock input.
Claim 6
Dependent Claim
30 words
The method of claim 1, further comprising the step of connecting a plurality of capacitors between said power circuit and said ground circuit to avoid excessive power and ground noise.
Claim 7
Dependent Claim
23 words
The method of claim 1, further including the step of connecting an external source to said circuits to provide power, ground and clock.
Claim 8
Dependent Claim
42 words
The method of claim 1 and further comprising: testing the integrated circuits by applying selected voltages to said power, ground and clock circuits; and detecting selected characteristics of the integrated circuits in response to said selected voltages using said infrared indicating circuit.
Claim 9
Independent Claim
158 words
A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising the steps of: forming a plurality of first lead lines on the wafer interconnected to at least one power input on the integrated circuits; forming a plurality of second lead lines on the wafer interconnected to at least one ground input on the integrated circuits, wherein said pluralities of first and second lead lines comprise a first metallization layer; forming a plurality of third lead lines on the wafer interconnected to a clock input on the integrated circuits, wherein said plurality of third lead lines comprise a second metallization layer; forming an insulator layer between said first and second metallization layers; providing power, ground and clock with a test head to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; and providing a detecting circuit to optically detect a test pass/fail condition for each integrated circuit.
Claim 10
Independent Claim
158 words
A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising the steps of: forming a plurality of first lead lines on the wafer interconnected to at least one power input on the integrated circuits; forming a plurality of second lead lines on the wafer interconnected to at least one ground input on the integrated circuits, wherein said pluralities of first and second lead lines comprise a first metallization layer; forming a plurality of third lead lines on the wafer interconnected to a clock input on the integrated circuits, wherein said plurality of third lead lines comprise a second metallization layer; forming an insulator layer between said first and second metallization layers; providing power, ground and clock with a test head to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; and providing a detecting circuit to optically detect a test pass/fail condition for each integrated circuit.
Claim 11
Dependent Claim
24 words
The method of claim 8, wherein the steps of forming lead lines comprise: metallizing the wafer; patterning said lines; and etching said patterned lines.
Claim 12
Independent Claim
146 words
A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising: a plurality of first lead lines formed on the wafer and interconnected to at least one power input on the integrated circuits; a plurality of second lead lines formed on the wafer and interconnected to at least one ground input on the integrated circuits; a plurality of third lead lines formed on the wafer and interconnected to a clock input on the integrated circuits, wherein said first and second lead lines comprise a second metallization layer, and said third lead line comprises a second metallization layer separated from said first metallization layer by an insulator; and a test head for providing power, ground and clock to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; wherein said test head further comprises an infrared detector.
Claim 13
Independent Claim
146 words
A method for simultaneously self-testing a plurality of integrated circuits on a semiconductor wafer, comprising: a plurality of first lead lines formed on the wafer and interconnected to at least one power input on the integrated circuits; a plurality of second lead lines formed on the wafer and interconnected to at least one ground input on the integrated circuits; a plurality of third lead lines formed on the wafer and interconnected to a clock input on the integrated circuits, wherein said first and second lead lines comprise a second metallization layer, and said third lead line comprises a second metallization layer separated from said first metallization layer by an insulator; and a test head for providing power, ground and clock to said first, second and third lead lines to simultaneously self-test the integrated circuits on the wafer; wherein said test head further comprises an infrared detector.
Claim 14
Dependent Claim
24 words
The apparatus of claim 10, wherein each of said plurality of first lead lines are connected together to form a wafer power input bus.
Claim 15
Dependent Claim
24 words
The apparatus of claim 10, wherein each of said plurality of second lead lines are connected together to form a wafer power input bus.
Claim 16
Dependent Claim
24 words
The apparatus of claim 10, wherein each of said plurality of third lead lines are connected together to form a wafer power input bus.
Claim 17
Dependent Claim
27 words
The apparatus of claim 10, further including a plurality of capacitors interconnected between said first lines and said second lines to avoid excessive power and ground noise.
Claim 18
Dependent Claim
46 words
The apparatus of claim 10, wherein said test head comprises: a platform; a power probe on said platform; a ground probe on said platform; and a clock probe on said platform to allow said test head to be positioned over the wafer to test circuits thereon.
Claim 19
Dependent Claim
25 words
The apparatus of claim 15, further comprising an infrared lens interconnected to said infrared detector for observing the circuits during testing to locate failed circuits.
Claim 20
Dependent Claim
22 words
The apparatus of claim 16, further including a wide-angle lens to allow the plurality of the integrated circuits to be viewed simultaneously.
Claim 21
Dependent Claim
18 words
The apparatus of claim 16, further including a scanner device to sequentially view the plurality of integrated circuits.
Claim 22
Dependent Claim
36 words
The apparatus of claim 15, further including a plurality of capacitor probes capable of connection between said plurality of first lead lines and said plurality of second lead lines to avoid excessive power and ground noise.
Claim 23
Dependent Claim
18 words
The apparatus of claim 10, wherein said test head further includes a dye marker to mark failed circuits.
Claim 24
Dependent Claim
20 words
The apparatus of claim 16, further comprising a resistor on each of the circuits to indicate a test pass/fail condition.
Claim 25
Dependent Claim
146 words
A semiconductor wafer for enabling self-testing of integrated circuits thereon, comprising: a power circuit interconnected to a power input on the integrated circuits; a first probe for supplying power to said power circuit; a ground circuit interconnected to a ground input on the integrated circuits; a second probe for supplying power to said ground circuit; a clock circuit interconnected to a clock input on the integrated circuits being operable to allow the integrated circuits to be simultaneously tested; a third probe for supplying power to said clock circuit; a plurality of capacitor probes insertable between said power circuit and said ground circuit to avoid excessive power and ground noise; a means for holding said first, second, third, and capacitor probes to allow placement over a wafer to be tested; and an indicating circuit, wherein said circuit optically indicates a test pass/fail condition for each integrated circuit.
Claim 26
Dependent Claim
146 words
A semiconductor wafer for enabling self-testing of integrated circuits thereon, comprising: a power circuit interconnected to a power input on the integrated circuits; a first probe for supplying power to said power circuit; a ground circuit interconnected to a ground input on the integrated circuits; a second probe for supplying power to said ground circuit; a clock circuit interconnected to a clock input on the integrated circuits being operable to allow the integrated circuits to be simultaneously tested; a third probe for supplying power to said clock circuit; a plurality of capacitor probes insertable between said power circuit and said ground circuit to avoid excessive power and ground noise; a means for holding said first, second, third, and capacitor probes to allow placement over a wafer to be tested; and an indicating circuit, wherein said circuit optically indicates a test pass/fail condition for each integrated circuit.
Claim 27
Dependent Claim
45 words
The wafer of claim 22 wherein said power circuit comprises: a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and a bus for allowing said lines to be powered by a single, external source.
Claim 28
Dependent Claim
45 words
The wafer of claim 22 wherein said ground circuit comprises: a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and a bus for allowing said lines to be grounded by a single, external source.
Claim 29
Dependent Claim
48 words
The wafer of claim 22 wherein said clock circuit comprises: a plurality of lead lines formed on the wafer during a metallization of the wafer extending between the integrated circuits; and a bus for allowing said lines to be provided with clock data from a single, external source.
Claim 30
Dependent Claim
27 words
The wafer of claim 22, further including a plurality of capacitors connected between said power circuit and said ground circuit to avoid excessive power and ground noise.
Claim 31
Dependent Claim
13 words
The wafer of claim 22 wherein said means for holding comprises a platform.
Claim 32
Dependent Claim
16 words
The wafer of claim 27, wherein said platform further includes means for marking failed integrated circuits.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-07-14 | 1996-01-13 | 1996-07-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-07-14 | 2000-01-13 | 2000-07-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-07-14 | 2004-01-13 | 2004-07-14 | $7700.00 | Window Closed / Lapsed |