US5397997A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Burn-in technologies for unpackaged integrated circuits
Assignee: nCHIP Inc
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Filing: 1993-05-06
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Granted: 1995-03-14
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Expires: 2013-05-06
Abstract
Abstract A device and method for burn-in of bare chips prior to assembly into a multichip module. Each die to be tested is positioned with its I/O pads positioned to face an interconnection burn-in test substrate which may be a silicon circuit board. Each die is temporarily electrically connected to the substrate by a deformable solder bump.
Inventors
- 👤 David Tuckerman
- 👤 Pradip Patel
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 09:19
CPC Classifications
G; G01; G01R; G01R31/00; G01R31/28; G01R31/2851; G01R31/2855; G01R31/286; G01R31/2863; H; H10; H10W; H10W72/00; H10W72/20; H10W72/29; H10W72/50; H10W72/531; H10W72/5363; H10W72/551; H10W72/552; H10W72/5522; H10W72/59; H10W72/851; H10W72/874; H10W72/884; H10W90/00; H10W90/701; H10W90/731; H10W90/734; H10W90/751; H10W90/754
Claims Analysis
Total Claims: 27
Claim 1
Independent Claim
125 words
A test apparatus for testing at least one integrated circuit having contact pads, the apparatus comprising: a test substrate including: (i) a base; (ii) a conducting plane on top of said base; (iii) an interconnect layer; (iv) an insulating layer disposed between the interconnect layer and said conducting plane; means for coupling the test substrate to a source of test signals; a plurality of electrically conductive non-rigid deformable bumps disposed between the interconnect layer of said test substrate and individual contact pads of the at least one integrated circuit to provide electrical contact between the test substrate and the at least one integrated circuit; and wherein at least one of said deformable bumps experiences permanent deformation when contacted by said at least one integrated circuit.
Claim 2
Dependent Claim
125 words
A test apparatus for testing at least one integrated circuit having contact pads, the apparatus comprising: a test substrate including: (i) a base; (ii) a conducting plane on top of said base; (iii) an interconnect layer; (iv) an insulating layer disposed between the interconnect layer and said conducting plane; means for coupling the test substrate to a source of test signals; a plurality of electrically conductive non-rigid deformable bumps disposed between the interconnect layer of said test substrate and individual contact pads of the at least one integrated circuit to provide electrical contact between the test substrate and the at least one integrated circuit; and wherein at least one of said deformable bumps experiences permanent deformation when contacted by said at least one integrated circuit.
Claim 3
Dependent Claim
17 words
The test apparatus of claim 1 wherein each of said electrically conductive deformable bumps comprises lead-indium solder.
Claim 4
Dependent Claim
24 words
The test apparatus of claim 1 wherein each of said electrically conductive deformable bumps is attached to the interconnect layer of said test substrate.
Claim 5
Dependent Claim
30 words
The test apparatus of claim 1 wherein each of said electrically conductive deformable bumps has a melting point less than a maximum temperature at which said test substrate retains functionality.
Claim 6
Dependent Claim
25 words
The test apparatus of claim 1 wherein each of said electrically conductive deformable bumps has a melting point temperature greater than a test operating temperature.
Claim 7
Dependent Claim
22 words
The test apparatus of claim 1 wherein the at least one integrated circuit comprises a plurality of integrated circuits on a wafer.
Claim 8
Dependent Claim
18 words
The test apparatus of claim 1 wherein said electrically conductive deformable bumps comprise reworkable electrically conductive deformable bumps.
Claim 9
Dependent Claim
21 words
The test apparatus of claim 1 further comprising a means for holding said integrated circuit in contact with said deformable bumps.
Claim 10
Dependent Claim
23 words
The test apparatus of claim 8 wherein said means for holding said integrated circuit in contact with said deformable bumps comprises a piston.
Claim 11
Dependent Claim
24 words
The test apparatus of claim 8 wherein said means for holding said integrated circuit in contact with said deformable bumps comprises a fluid-filled bladder.
Claim 12
Dependent Claim
41 words
The test apparatus of claim 8 wherein said means for holding said integrated circuit in contact with said deformable bumps comprises a means for forming a vacuum between a surface of said test substrate and a surface of said integrated circuit.
Claim 13
Dependent Claim
18 words
The test apparatus of claim 1 further comprising a means for regulating the temperature of said integrated circuit.
Claim 14
Dependent Claim
54 words
The test apparatus of claim 1 further comprising a temperature regulator including: (i) a heat sink attached to said substrate; (ii) a temperature measuring device mounted on said heat sink; and (iii) a control system coupled to said temperature measuring device and to said heat sink for regulating the temperature of said integrated circuit.
Claim 15
Dependent Claim
15 words
The test apparatus of claim 1 wherein said electrically conductive deformable bumps comprise lead-tin solder.
Claim 16
Dependent Claim
30 words
The test apparatus of claim 1 wherein a given one of said plurality of electrically conductive deformable bumps is coined to prevent said given bump from contacting said contact pad.
Claim 17
Dependent Claim
16 words
The test apparatus of claim 1, wherein said plurality of deformable bumps comprise reflowed deformable bumps.
Claim 18
Independent Claim
77 words
A method for testing an integrated circuit comprising the steps of: forming a plurality of non-rigid, deformable, electrically conductive bumps on an interconnect layer of a test substrate; placing contact pads of the integrated circuit in removable contact with said non-rigid deformable electrically conductive bumps and causing at least one of said non-rigid deformable electrically conductive bumps to experience permanent deformation; and supplying a plurality of test signals to said test substrate to exercise said integrated circuit.
Claim 19
Independent Claim
77 words
A method for testing an integrated circuit comprising the steps of: forming a plurality of non-rigid, deformable, electrically conductive bumps on an interconnect layer of a test substrate; placing contact pads of the integrated circuit in removable contact with said non-rigid deformable electrically conductive bumps and causing at least one of said non-rigid deformable electrically conductive bumps to experience permanent deformation; and supplying a plurality of test signals to said test substrate to exercise said integrated circuit.
Claim 20
Dependent Claim
47 words
The method of claim 17 wherein the step of placing said contact pad in removable contact with said bumps comprises the step of: creating a vacuum between a top surface of said substrate and a surface of said integrated circuit adjacent said top surface of said substrate.
Claim 21
Dependent Claim
41 words
The method of claim 17 wherein the step of placing said contact pad in removable contact with said bumps comprises the step of: applying pressure, to a top surface of a device wafer containing said integrated circuit therein, with a piston.
Claim 22
Dependent Claim
43 words
The method of claim 17 wherein the step of placing said contact pad in removable contact with said bumps comprises the step of: applying pressure, to a top surface of a device wafer containing said integrated circuit therein, with a fluid filled bladder.
Claim 23
Dependent Claim
32 words
The method of claim 17 further comprising the step of actively controlling a temperature of said test substrate and said integrated circuit whereby a burn-in test is conducted without a burn-in oven.
Claim 24
Dependent Claim
21 words
The method of claim 17 further comprising the step of: reflowing said non-rigid deformable bumps to form new non-rigid deformable bumps.
Claim 25
Dependent Claim
58 words
The method of claim 17, wherein the integrated circuit comprises a plurality of integrated circuits on a device wafer and further comprising the step of ablating a selected contact pad using a laser to prevent operation of a given one of said plurality of integrated circuits during testing of said device wafer having said plurality of integrated circuits.
Claim 26
Independent Claim
134 words
A method for burning-in a plurality of integrated circuits comprising the steps of: forming a plurality of non-rigid, deformable, electrically conductive bumps on an interconnect layer of a test substrate; placing contact pads of a first integrated circuit in removable contact with said non-rigid, deformable electrically conductive bumps and causing at least one of said non-rigid deformable electrically conductive bumps to experience permanent deformation; supplying a plurality of test signals to said test substrate to exercise said first integrated circuit; reflowing said deformable bumps, after said first integrated circuit has been tested, to form a new non-rigid, deformable, electrically conductive bumps; placing a contact pad of a second integrated circuit in contact with said new non-rigid, deformable electrically conductive bumps; and supplying test signals to said test substrate to exercise said second integrated circuit.
Claim 27
Independent Claim
134 words
A method for burning-in a plurality of integrated circuits comprising the steps of: forming a plurality of non-rigid, deformable, electrically conductive bumps on an interconnect layer of a test substrate; placing contact pads of a first integrated circuit in removable contact with said non-rigid, deformable electrically conductive bumps and causing at least one of said non-rigid deformable electrically conductive bumps to experience permanent deformation; supplying a plurality of test signals to said test substrate to exercise said first integrated circuit; reflowing said deformable bumps, after said first integrated circuit has been tested, to form a new non-rigid, deformable, electrically conductive bumps; placing a contact pad of a second integrated circuit in contact with said new non-rigid, deformable electrically conductive bumps; and supplying test signals to said test substrate to exercise said second integrated circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-03-13 | 1998-09-12 | 1999-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-03-13 | 2002-09-12 | 2003-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-03-13 | 2006-09-12 | 2007-03-14 | $7700.00 | Window Closed / Lapsed |