Probe for wafer burn-in test system

Claim 1

A test apparatus for testing over a range of temperatures electronic integrated circuits residing on a test wafer, comprising: a probe assembly for transmitting test signals to test contacts on the circuits residing on the test wafer, said probe assembly comprising upper and lower guide elements spaced apart from and in fixed relationship to each other, each of said guide elements having a plurality of holes therein and comprising a layer of silicon adjacent to a layer of electrically insulating, photolithographically patternable material, and a plurality of probes extending through and beyond said plurality of holes in each of said guide elements, each probe in said plurality having a first end connected with a source of test signals and a second end adapted to contact the test contacts on the test wafer, each of said layers of photolithographically patternable material having an inner surface facing one of said layers of silicon, each of said layers of silicon having an inner surface facing one of said layers of photolithographically patternable material, the adjacent layers of silicon and photolithographically patternable material in each of the upper and lower guide elements being joined by fused layers of metal deposition deposited on each of said inner surfaces of photolithographically patternable material and each of said inner surfaces of silicon; an alignment mechanism for aligning said probe assembly with the test contacts; a securing mechanism for securing the position of said test wafer with respect to said probe assembly when said probe assembly and the test contacts are aligned; and a contacting mechanism for contacting said second ends of said probes with the test contacts.

Claim 24

A method of forming a test probe assembly for environmentally testing electronic circuitry, comprising the steps of: providing first and second layers of silicon having an array of chemically etched holes therein; providing first and second layers of photolithographically patternable material having an array of chemically etched holes therein, said photolithographically patternable material array of holes having a similar pattern to said silicon array of holes; depositing a thin metallic film onto one side of each of said first and second layers of silicon; depositing a thin metallic film onto one side of each of said first and second layers of photolithographically patternable material; positioning said first layer of silicon with respect to said first layer of photolithographically patternable material so that said arrays of holes in each of said first layers are aligned and so that said thin metallic films deposited onto each of said first layers face each other; positioning said second layer of silicon with respect to said second layer of photolithographically patternable material so that said arrays of holes in each of said second layers are aligned and so that said thin metallic films deposited onto each of said second layers face each other; heat treating said positioned first layers and said positioned second layers so that said facing thin metallic films fuse to form a metallic bond; attaching said first layer of silicon to said second layer of silicon with at least one spacer to maintain said first layer of silicon spaced apart from and in fixed relationship to said second layer of silicon; providing a device interface board which is connectable to the apparatus for testing electronic circuitry and which carries test signals outputted by the apparatus; attaching a plurality of test probes to said device interface board, each of said test probes having a length greater than the combined widths of said spacer, said first and second photolithographically patternable material layers, and said first and second silicon layers; and inserting said extending test probes through said aligned arrays of holes in said positioned first layers and said positioned second layers to complete said test probe assembly.

Claim 25

A method of forming a test probe assembly for environmentally testing electronic circuitry, comprising the steps of: providing first and second layers of silicon having an array of chemically etched holes therein; providing first and second layers of photolithographically patternable material having an array of chemically etched holes therein, said photolithographically patternable material array of holes having a similar pattern to said silicon array of holes; depositing a thin metallic film onto one side of each of said first and second layers of silicon; depositing a thin metallic film onto one side of each of said first and second layers of photolithographically patternable material; positioning said first layer of silicon with respect to said first layer of photolithographically patternable material so that said arrays of holes in each of said first layers are aligned and so that said thin metallic films deposited onto each of said first layers face each other; positioning said second layer of silicon with respect to said second layer of photolithographically patternable material so that said arrays of holes in each of said second layers are aligned and so that said thin metallic films deposited onto each of said second layers face each other; heat treating said positioned first layers and said positioned second layers so that said facing thin metallic films fuse to form a metallic bond; attaching said first layer of silicon to said second layer of silicon with at least one spacer to maintain said first layer of silicon spaced apart from and in fixed relationship to said second layer of silicon; providing a device interface board which is connectable to the apparatus for testing electronic circuitry and which carries test signals outputted by the apparatus; attaching a plurality of test probes to said device interface board, each of said test probes having a length greater than the combined widths of said spacer, said first and second photolithographically patternable material layers, and said first and second silicon layers; and inserting said extending test probes through said aligned arrays of holes in said positioned first layers and said positioned second layers to complete said test probe assembly.