US4994735A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Flexible tester surface for testing integrated circuits
Assignee: DRI TECHNOLOGY Corp A CORP OF CALIFORNIA
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Filing: 1989-11-14
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Granted: 1991-02-19
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Expires: 2009-11-14
Abstract
Abstract The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silcon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.
Inventors
- 👤 Glenn J. Leedy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 13:20
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/317; G01R31/3181; G01R31/319; G01R31/31903; G01R31/31912; G03; G03F; G03F7/00; G03F7/70; G03F7/70425; G03F7/70466; G03F7/70483; G03F7/70605; G03F7/70653; G03F7/70658; G11; G11C; G11C29/00; G11C29/006; H10W; H10W70/00; H10W70/60; H10W70/62; H10W70/63
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
90 words
A tester surface for integrated circuits for contacting contact points of logic units on a surface of a semiconductor wafer, said tester surface comprising: at least one layer, said layer comprising a dielectric predominantly silicon flexible material and having a thickness of no greater than fifteen microns; a plurality of conductive vias formed in said thin flexible material; and a thin film of patterned conductive metal deposited on said thin flexible material and in said vias to form conductive traces, including probe points for test contacting with said contact points.
Claim 2
Dependent Claim
90 words
A tester surface for integrated circuits for contacting contact points of logic units on a surface of a semiconductor wafer, said tester surface comprising: at least one layer, said layer comprising a dielectric predominantly silicon flexible material and having a thickness of no greater than fifteen microns; a plurality of conductive vias formed in said thin flexible material; and a thin film of patterned conductive metal deposited on said thin flexible material and in said vias to form conductive traces, including probe points for test contacting with said contact points.
Claim 3
Dependent Claim
14 words
The tester surface of claim 1, wherein said material comprises low stress silicon dioxide.
Claim 4
Dependent Claim
21 words
The tester surface of claim 1, wherein said material is comprised of low stress silicon dioxide formed by chemical vapor deposition.
Claim 5
Dependent Claim
35 words
The tester surface of claim 1, further comprising a rigid annular support fixed to the perimeter of said test surface, on the side of said test surface opposite to the side having said probe points.
Claim 6
Dependent Claim
17 words
The tester surface of claim 1, including more than one thousand probe points on the tester surface.
Claim 7
Dependent Claim
19 words
The tester surface of claim 1, wherein the probe points have a diameter of about 2 to 4 microns.
Claim 8
Dependent Claim
23 words
The tester surface of claim 6, wherein the low stress silicon dioxide has a surface stress of about 10 5 dynes/cm 2 .
Claim 9
Dependent Claim
23 words
The tester surface of claim 1, further comprising a second thin film of conductive metal formed overlying said thin film and insulated therefrom.
Claim 10
Dependent Claim
19 words
The tester surface of claim 1, further comprising logic circuitry connected to said probe points by said conductive traces.
Claim 11
Dependent Claim
22 words
The tester surface of claim 1, further comprising logic circuitry mounted on said tester surface and electrically connected to said conductive traces.
Claim 12
Dependent Claim
24 words
The tester surface of claim 1, further comprising integrated circuit die mounted directly on said tester surface and electrically connected to said conductive traces.
Claim 13
Dependent Claim
29 words
The tester surface of claim 10, wherein a distance between at least one of said probe points and said logic circuitry is less than two and a half inches.
Claim 14
Dependent Claim
18 words
The tester surface of claim 1, wherein the probe points have a diameter no greater than one mil.
Claim 15
Dependent Claim
21 words
The tester surface of claim 9, wherein the logic circuitry is directly connected to said probe points by said conductive traces.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-02-18 | 1994-08-20 | 1995-02-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-02-18 | 1998-08-20 | 1999-02-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-02-18 | 2002-08-20 | 2003-02-19 | $7700.00 | Window Closed / Lapsed |