US5532610A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for testing semicondctor wafer
Assignee: NEC Corp
•
Filing: 1994-08-25
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Granted: 1996-07-02
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Expires: 2014-08-25
Abstract
Abstract The apparatus for collectively burning-in or testing a plurality of semiconductor chips disposed on a wafer without dicing the chips into individuals, the apparatus including a testing substrate, an active circuit disposed on the testing substrate for activating chips disposed on the wafer to be tested, a plurality of pads disposed on the testing substrate and positioned so that the pads are disposed in alignment with bonding pads of the chips disposed on the wafer when the testing substrate is overlaid on the wafer, and an anisotropic conductive layer disposed on the pads.
Inventors
- 👤 Tohru Tsujide
- 👤 Toshiyasu Hishii
- 👤 Kazuo Nakaizumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 02:41
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
136 words
An apparatus for testing or burning-in a plurality of semiconductor chips disposed on a wafer, said apparatus comprising: a testing substrate; an active circuit disposed on said testing substrate for activating chips disposed on a wafer to be tested; a plurality of pads disposed on said testing substrate and positioned so that said pads are disposed in alignment with bonding pads of said chips disposed on said wafer when said testing substrate is engaged to said wafer; an anisotropic conductive layer disposed on said pads; and means electrically connected to said testing substrate for testing said wafer, and including a circuit integrated on said testing substrate for rapidly testing a plurality of chips formed on said wafer at the same time and a memory integrated on said testing substrate for storing the results of the test.
Claim 2
Independent Claim
136 words
An apparatus for testing or burning-in a plurality of semiconductor chips disposed on a wafer, said apparatus comprising: a testing substrate; an active circuit disposed on said testing substrate for activating chips disposed on a wafer to be tested; a plurality of pads disposed on said testing substrate and positioned so that said pads are disposed in alignment with bonding pads of said chips disposed on said wafer when said testing substrate is engaged to said wafer; an anisotropic conductive layer disposed on said pads; and means electrically connected to said testing substrate for testing said wafer, and including a circuit integrated on said testing substrate for rapidly testing a plurality of chips formed on said wafer at the same time and a memory integrated on said testing substrate for storing the results of the test.
Claim 3
Dependent Claim
36 words
An apparatus in accordance with claim 1, further comprising a flexible print substrate, wherein said means for testing said wafer further includes a tester head electrically connected to said testing substrate through said flexible print substrate.
Claim 4
Independent Claim
27 words
An apparatus in accordance with claim, 1, wherein said testing substrate is made of material having a thermal expansion coefficient not more than 13×10 -6 per degree.
Claim 5
Dependent Claim
12 words
An apparatus in accordance with claim 3, wherein said material is silicon.
Claim 6
Dependent Claim
57 words
An apparatus in accordance with claim 1, wherein said active circuit includes a circuit for supplying an electrical load to said chips disposed on said wafer, a circuit for controlling an electrical load to be supplied to said chips disposed on said wafer, and a circuit for selecting a chip among said chips disposed on said wafer.
Claim 7
Dependent Claim
26 words
An apparatus in accordance with claim 1, further comprising a glass substrate, wherein said testing substrate has said glass substrate secured to a bottom surface thereof.
Claim 8
Dependent Claim
30 words
An apparatus in accordance with claim 1, wherein said testing substrate is provided with a plurality of apertures serving as alignment marks for aligning said wafer with said testing substrate.
Claim 9
Dependent Claim
29 words
An apparatus in accordance with claim 7, wherein each of said apertures has a quadrangular pyramid shaped (111) plane formed by anisotropic-etching a silicon wafer having a (100) plane.
Claim 10
Dependent Claim
34 words
An apparatus in accordance with claim 1, wherein said active circuit includes means for receiving an external signal to thereby activate a chip identified with said external signal among chips disposed on said wafer.
Claim 11
Dependent Claim
19 words
An apparatus in accordance with claim 1 further comprising means for compressively securing said wafer to said testing substrate.
Claim 12
Dependent Claim
17 words
An apparatus in accordance with claim 1 further comprising means for providing thermal stress with said wafer.
Claim 13
Dependent Claim
24 words
An apparatus in accordance with claim 1 further comprising a bath for containing therein said apparatus to maintain said apparatus at a constant temperature.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-07-02 | 2000-01-01 | 2000-07-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-07-02 | 2004-01-01 | 2004-07-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-07-02 | 2008-01-01 | 2008-07-02 | $7700.00 | Window Closed / Lapsed |