US4956602A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Wafer scale testing of redundant integrated circuit dies
Assignee: Amber Engineering Inc
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Filing: 1989-02-14
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Granted: 1990-09-11
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Expires: 2009-02-14
Abstract
Abstract A wafer scale test system for testing redundant integrated circuit dies formed on a semiconductor wafer includes wafer scale test pads formed on the wafer and interchip multiplexor means for directing test signals applied to the wafer scale test pads to the individual integrated circuit dies. The interchip multiplexor means includes an input/output buffer circuit for receiving test signals from the wafer pads and applying the test signals to selected interchip multiplexor lines routed to the individual circuit dies. Readouts from output pads on said integrated circuit dies are routed back through the input/output buffer circuit to the wafer test pads to provide test output signals. Low cross-section connecting means are provided across dicing lanes between the integrated circuit die contact pads and the interchip multiplexor lines to avoid shorting during the dicing operation. Additionally, line protection circuits are provided to prevent destruction of the integrated circuuit dies should shorting occur during dicing. The integrated circuit dies and wafer scale test system may optionally be partitioned into several separate groups to prevent faults in the interchip multiplexor system from rendering the entire wafer useless.
Inventors
- 👤 William J. Parrish
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 03:55
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/23; H10P74/232; G; G01; G01R; G01R31/00; G01R31/28; G01R31/282; G01R31/2831; G01R31/317; G01R31/31712; G01R31/31715; G01R31/3181; G01R31/3185; G01R31/318505; G01R31/318511; G06; G06F; G06F11/00; G06F11/22; G06F11/26; G11; G11C; G11C29/00; G11C29/006; G06F11/2273
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
188 words
A redundant die wafer test system, comprising: a semiconductor substrate having an upper major surface; a plurality of integrated circuit dies formed on said substrate in separate regions of said upper major surface, said separate regions being separated by a plurality of dicing lanes, each of said integrated circuit dies having a plurality of electrical bonding pads; a plurality of wafer test pads formed on said substrate; interchip multiplexor means, coupled to said plurality of electrical bonding pads and said plurality of wafer test pads, for providing electrical test signals from said wafer test pads to said plurality of integrated circuit dies and providing output test signals from said dies to said wafer test pads said interchip multiplexor means including a plurality of interchip multiplexor lines formed on said upper major surface of said semiconductor substrate and a plurality of electrical leads coupling said electrical bonding pads to said interchip multiplexor lines, said electrical leads traversing said dicing lanes on said upper major surface of said semiconductor substrate; and circuit protection means for disconnecting said electrical bonding pads from said multiplexor lines after dicing along said dicing lanes.
Claim 2
Dependent Claim
188 words
A redundant die wafer test system, comprising: a semiconductor substrate having an upper major surface; a plurality of integrated circuit dies formed on said substrate in separate regions of said upper major surface, said separate regions being separated by a plurality of dicing lanes, each of said integrated circuit dies having a plurality of electrical bonding pads; a plurality of wafer test pads formed on said substrate; interchip multiplexor means, coupled to said plurality of electrical bonding pads and said plurality of wafer test pads, for providing electrical test signals from said wafer test pads to said plurality of integrated circuit dies and providing output test signals from said dies to said wafer test pads said interchip multiplexor means including a plurality of interchip multiplexor lines formed on said upper major surface of said semiconductor substrate and a plurality of electrical leads coupling said electrical bonding pads to said interchip multiplexor lines, said electrical leads traversing said dicing lanes on said upper major surface of said semiconductor substrate; and circuit protection means for disconnecting said electrical bonding pads from said multiplexor lines after dicing along said dicing lanes.
Claim 3
Dependent Claim
92 words
A redundant die wafer test system as set out in claim 1 wherein said interchip multiplexor means comprises: a plurality of interchip multiplexor lines formed on said upper major surface of said semiconductor substrate; and input/output multiplexor means coupled to said wafer test pads and said interchip multiplexor lines for receiving test signals applied to said wafer test pads and applying said test signals to selected interchip multiplexor lines and for receiving readout signals from said interchip multiplexor lines and applying said readout signals to selected ones of said wafer test pads.
Claim 4
Dependent Claim
27 words
A redundant die wafer test system as set out in claim 1 whereinsaid integrated circuit dies are infrared focal plane array signal processing and readout integrated circuits.
Claim 5
Dependent Claim
153 words
A redundant die wafer test system, comprising: a semiconductor substrate having an upper major surface; a plurality of integrated circuit dies formed on said substrate in separate regions of said upper major surface, said separate regions being separated by a plurality of dicing lanes, each of said integrated circuit dies having a plurality of electrical bonding pads; a plurality of wafer test pads formed on said substrate; and interchip multiplexor means, coupled to said plurality of electrical bonding pads and said plurality of wafer test pads, for providing electrical test signals from said wafer test pads to said plurality of integrated circuit dies and providing output test signals rom said dies to said wafer test pads; wherein said integrated circuit dies are partitioned on said semiconductor substrate in a plurality of groups and wherein said wafer test pads and said interchip multiplexor means are separately provided for each group of integrated circuit dies.
Claim 6
Dependent Claim
153 words
A redundant die wafer test system, comprising: a semiconductor substrate having an upper major surface; a plurality of integrated circuit dies formed on said substrate in separate regions of said upper major surface, said separate regions being separated by a plurality of dicing lanes, each of said integrated circuit dies having a plurality of electrical bonding pads; a plurality of wafer test pads formed on said substrate; and interchip multiplexor means, coupled to said plurality of electrical bonding pads and said plurality of wafer test pads, for providing electrical test signals from said wafer test pads to said plurality of integrated circuit dies and providing output test signals rom said dies to said wafer test pads; wherein said integrated circuit dies are partitioned on said semiconductor substrate in a plurality of groups and wherein said wafer test pads and said interchip multiplexor means are separately provided for each group of integrated circuit dies.
Claim 7
Dependent Claim
20 words
A wafer scale test system as set out in claim 4 wherein said input/output buffer circuit comprises a demultiplexor circuit.
Claim 8
Dependent Claim
27 words
A wafer scale test system as set out in claim 4 wherein said integrated circuit dies and said input/output buffer circuits are complimentary metal oxide semiconductor circuits.
Claim 9
Dependent Claim
26 words
A wafer scale test system as set out in claim 4 wherein said integrated circuit dies are analog infrared focal plane array readout integrated circuit dies.
Claim 10
Dependent Claim
31 words
A wafer scale test system as set out in claim 4 wherein said wafer scale test pads, said integrated circuit dies and said interchip multiplexor lines are partitioned into separate groups.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-09-10 | 1994-03-12 | 1994-09-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-09-10 | 1998-03-12 | 1998-09-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-09-10 | 2002-03-12 | 2002-09-11 | $7700.00 | Window Closed / Lapsed |