US5089772A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for testing semiconductor integrated circuits and method of testing the same
Assignee: MARTEC Corp A CORPORATION OF JAPAN
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Filing: 1990-03-09
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Granted: 1992-02-18
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Expires: 2010-03-09
Abstract
Abstract Tests of a semiconductor IC is conducted first by bringing a plurality of conductive pattern circuits formed on an insulator sheet into contact with a plurality of bump electrodes formed on a substrate of the semiconductor, second by connecting a plurality of signal transmission pattern circuits formed on a transmission circuit substrate with each conductive pattern circuit of the insulator sheet, and then by connecting the transmission circuit substrate with a body of the testing device. A probing test can be simplified since there is no need to manually adjust positions of conventional probe needles. Further, semiconductor ICs having a lot of bump electrodes can be test without being damaged.
Inventors
- 👤 Kenzo Hatada
- 👤 Takeshi Ishihara
- 👤 Nobuaki Suzuki
- 👤 Satowaka Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 17:26
CPC Classifications
G; G01; G01R; G01R1/00; G01R1/02; G01R1/06; G01R1/067; G01R1/073; G01R1/07307; G01R1/0735
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
184 words
A device for testing a semiconductor integrated circuit, said device comprising: an insulator sheet having an upper surface, a lower surface, and a peripheral edge and said insulator sheet having a plurality of conductive pattern circuits which are disposed at the lower surface of the insulator sheet and which make contact with said semiconductor IC; and a transmission circuit substrate laterally disposed with respect to the peripheral edge of said insulator sheet so that only said conductive pattern circuits disposed at the lower surface of the insulator sheet make contact with said semiconductor IC and said transmission circuit substrate having a plurality of signal transmission pattern circuits which are connected with each conductive pattern circuit of said insulator sheet, said signal transmission pattern circuits being disposed in parallel or radially with respect to each other; wherein, said transmission circuit substrate is flexible and connected with a body of a testing device, and said insulator sheet is formed of a rigid deformation resistant material and arranged to be substantially parallel with said semiconductor IC when the conductive pattern circuits make contact with said semiconductor IC.
Claim 2
Independent Claim
184 words
A device for testing a semiconductor integrated circuit, said device comprising: an insulator sheet having an upper surface, a lower surface, and a peripheral edge and said insulator sheet having a plurality of conductive pattern circuits which are disposed at the lower surface of the insulator sheet and which make contact with said semiconductor IC; and a transmission circuit substrate laterally disposed with respect to the peripheral edge of said insulator sheet so that only said conductive pattern circuits disposed at the lower surface of the insulator sheet make contact with said semiconductor IC and said transmission circuit substrate having a plurality of signal transmission pattern circuits which are connected with each conductive pattern circuit of said insulator sheet, said signal transmission pattern circuits being disposed in parallel or radially with respect to each other; wherein, said transmission circuit substrate is flexible and connected with a body of a testing device, and said insulator sheet is formed of a rigid deformation resistant material and arranged to be substantially parallel with said semiconductor IC when the conductive pattern circuits make contact with said semiconductor IC.
Claim 3
Dependent Claim
26 words
A device for testing a semiconductor IC as defined in claim 1 wherein said insulator sheet is covered with a conductor on the upper surface thereof.
Claim 4
Dependent Claim
66 words
A device for testing a semiconductor IC as defined in claim 1 wherein said insulator sheet is composed of transparent material and said conductive pattern circuits are composed of a transparent conductor or a metal conductor at least in portions of said insulator sheet and conductive pattern circuits where said conductive pattern circuits make contact with a plurality of bump electrodes provided on the semiconductor IC.
Claim 5
Dependent Claim
36 words
A device for testing a semiconductor IC as defined in claim 3, wherein said conductive pattern circuits are planar at least in portions thereof where contact is made with each bump electrode of the semiconductor IC.
Claim 6
Dependent Claim
80 words
A device for testing a semiconductor IC as defined in claim 1 wherein said insulator sheet is covered with a conductor on the upper surface thereof, and said insulator sheet is composed of transparent material and said conductive pattern circuits are composed of a transparent conductor or a metal conductor at least in portions of said insulator sheet and conductive pattern circuits where said conductive pattern circuits make contact with a plurality of bump electrodes provided on the semiconductor IC.
Claim 7
Dependent Claim
36 words
A device for testing a semiconductor IC as defined in claim 5, wherein said conductive pattern circuits are planar at least in portions thereof where contact is made with each bump electrode of the semiconductor IC.
Claim 8
Dependent Claim
29 words
A device for testing a semiconductor IC as defined in claim 1, wherein bump electrodes are formed on said conductive pattern circuits for making contact with said semiconductor IC.
Claim 9
Dependent Claim
29 words
A device for testing a semiconductor IC as defined in claim 1, wherein bump electrodes are formed on said semiconductor IC for making contact with said conductive pattern circuit.
Claim 10
Independent Claim
157 words
A method of testing a semiconductor integrated circuit comprising the steps of: providing a rigid deformation resistant insulator sheet having an upper surface, a lower surface, and a peripheral edge; bringing a plurality of conductive pattern circuits formed on the lower surface of said rigid deformation resistant insulator sheet into contact with a plurality of bump electrodes formed on a substrate of the semiconductor IC in a manner such that the insulator sheet is substantially parallel with said substrate; connecting a plurality of signal transmission pattern circuits formed on a flexible transmission circuit substrate with each conductive pattern circuit of said insulator sheet where the flexible transmission circuit substrate is laterally disposed with respect to the peripheral edge of the insulating sheet so that only said conductive pattern circuits disposed at the lower surface of the insulator sheet make contact with said semiconductor IC; and connecting said transmission circuit substrate with a body of a testing device.
Claim 11
Independent Claim
157 words
A method of testing a semiconductor integrated circuit comprising the steps of: providing a rigid deformation resistant insulator sheet having an upper surface, a lower surface, and a peripheral edge; bringing a plurality of conductive pattern circuits formed on the lower surface of said rigid deformation resistant insulator sheet into contact with a plurality of bump electrodes formed on a substrate of the semiconductor IC in a manner such that the insulator sheet is substantially parallel with said substrate; connecting a plurality of signal transmission pattern circuits formed on a flexible transmission circuit substrate with each conductive pattern circuit of said insulator sheet where the flexible transmission circuit substrate is laterally disposed with respect to the peripheral edge of the insulating sheet so that only said conductive pattern circuits disposed at the lower surface of the insulator sheet make contact with said semiconductor IC; and connecting said transmission circuit substrate with a body of a testing device.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-02-17 | 1995-08-19 | 1996-02-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-02-17 | 1999-08-19 | 2000-02-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-02-17 | 2003-08-19 | 2004-02-18 | $7700.00 | Window Closed / Lapsed |