US5617577A
Expired / Lapsed
US
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Advanced parallel array processor I/O connection
Assignee: International Business Machines Corp
•
Filing: 1995-03-08
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Granted: 1997-04-01
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Expires: 2015-03-08
Abstract
Abstract A fast I/O for a multi-PME computer system provides a way to break into a network coupling to alternate network couplings. The system coupling is called a zipper. Our I/O zipper concept can be used to implement the concept that the port into a node could be driven by the port out of a node or by data coming from the system bus. Conversely, data being put out of a node would be available to both the input to another node and to the system bus. Outputting data to both the system bus and another node is not done simultaneously but in different cycles. The zipper passes data into and out of a network of interconnected nodes is used in a system of interconnecting nodes in a mesh, rings of wrapped tori. such that there is no edge to the network, the zipper mechanism logically breaks the the rings along a dimension orthogonal to the rings such that an edge to the network is established. The coupling dynamically toggles the network between a network without an edge and a network with an edge. Data passes into the network or out of the network through the edge when it is active, and the coupling permits dispersal of data entering the network or collection of data leaving the network such that the data rate through the edge matches both the sustained and peak data rates of the system external to the network.
Inventors
- 👤 Thomas N. Barker
- 👤 Clive A. Collins
- 👤 Michael C. Dapp
- 👤 James W. Dieffenderfer
- 👤 Donald G. Grice
- 👤 Billy J. Knowles
- 👤 Donald M. Lesmeister
- 👤 Richard E. Nier
- 👤 Eric E. Retter
- 👤 David B. Rolfe
- 👤 Vincent J. Smoral
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 21:15
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/483; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17337; G06F15/17343; G06F15/17356; G06F15/17368; G06F15/17381; G06F15/76; G06F15/80; G06F15/8007
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
180 words
A computer system, comprising: a plurality of nodes interconnected as a multi-dimensional network with parallel communication paths between processor-memory elements (PME's) each having a processor and a local memory along communication paths providing a processing array, each node comprising a plurality of PME's having communication paths to other PME's; an array director including: an application program interface for receiving and translating commands and data directed to said processing array; a cluster synchronizer; a cluster controller; and a zipper for breaking node connections and providing I/O communications to nodes; wherein the cluster synchronizer and the cluster controller route data and commands to appropriate clusters and provide load balancing among clusters; wherein the computer system is organized as a massively parallel machine with nodes interconnected as a multi-dimensional network cluster with parallel communication paths between PME's along communication paths both internal and external to a node, and further comprising means for breaking communication paths between PME's providing external I/O communication; wherein said processing array has rings for communication which can be broken to provide an interface for communications external to a node.
Claim 2
Dependent Claim
180 words
A computer system, comprising: a plurality of nodes interconnected as a multi-dimensional network with parallel communication paths between processor-memory elements (PME's) each having a processor and a local memory along communication paths providing a processing array, each node comprising a plurality of PME's having communication paths to other PME's; an array director including: an application program interface for receiving and translating commands and data directed to said processing array; a cluster synchronizer; a cluster controller; and a zipper for breaking node connections and providing I/O communications to nodes; wherein the cluster synchronizer and the cluster controller route data and commands to appropriate clusters and provide load balancing among clusters; wherein the computer system is organized as a massively parallel machine with nodes interconnected as a multi-dimensional network cluster with parallel communication paths between PME's along communication paths both internal and external to a node, and further comprising means for breaking communication paths between PME's providing external I/O communication; wherein said processing array has rings for communication which can be broken to provide an interface for communications external to a node.
Claim 3
Dependent Claim
28 words
The computer system of claim 1, wherein breaking of said rings provides a number of network edges equal to the number of orthogonal logical breaks of said rings.
Claim 4
Dependent Claim
46 words
The computer system of claim 2, wherein: said rings connect said nodes in an multi-dimensional orthogonal manner; orthogonal logical breaking of the rings occurs in a plurality of orthogonal dimensions; and data is passed into and out of said network through the multi-dimensional orthogonal ring breaks.
Claim 5
Dependent Claim
72 words
The computer system of claim 3, wherein said nodes operate in normal and circuit switched modes; normal node providing for data passage through said network edge into or out of memory of a node on said network edge; and circuit switched mode providing for data passage through said network edge and a node on said network edge and into or out of memory of a node not located on said network edge.
Claim 6
Dependent Claim
30 words
The computer system of claim 4, wherein data is passed through said network edge and through a plurality of nodes before going into or out of memory of a node.
Claim 7
Dependent Claim
57 words
A computer system according to claim 1, wherein nodes are coupled to other nodes as a 4 d modified hypercube providing eight external ports, with nodes connected via ports to form a ring, and rings being interconnected as rings of rings, and further comprising means for logically breaking rings to provide an edge for external I/O communication.
Claim 8
Dependent Claim
45 words
A computer system according to claim 1, further providing a modified hypercube interconnection of nodes having a topology of rings within rings and wherein rings are logically broken and two ends of a broken ring are connected for external I/O communication as a logical operation.
Claim 9
Dependent Claim
65 words
A computer system according to claim 1, further comprising a broadcast bus connected to said plurality of nodes and an I/O interface for the processor array which exists as a separate interface into the PME's, said I/O interface being established on at least one edge of a hypercube network and connected to said broadcast bus at multiple nodes in the network and in multiple directions.
Claim 10
Dependent Claim
41 words
A computer system according to claim 1, further comprising: a plurality of processor-memory elements (PME's) having communication paths to other PME's and a node identity; wherein said processing array has interfaces to attach external devices to PME's of said processing array.
Claim 11
Dependent Claim
271 words
A network data transfer apparatus, comprising: a network comprising rings of toroidally interconnected nodes, each of said nodes comprising a plurality of interconnected processor-memory elements (PME's) having a processor and a local memory; means for logically breaking said rings along a dimension orthogonal to said rings establishing a network edge; means for dynamic toggling between an edgeless network and an edged network; and means for data transfer into and out of said network through said network edge; wherein breaking of said rings provides a number of network edges equal to the number of orthogonal logical breaks of said rings; wherein said rings connect said nodes in an multi-dimensional orthogonal manner, orthogonal logical breaking of the rings occurs in a plurality of orthogonal dimensions, and data is passed into and out of said network through the multi-dimensional orthogonal ring breaks; wherein said nodes operate in normal and circuit switched modes; normal node providing for data passage through said network edge into or out of memories of a node on said network edge; and circuit switched mode providing for data passage through said network edge and a node on said network edge and into or out of memories of a node not located on said network edge; wherein data is passed through said network edge and through a plurality of nodes before going into or out of memories of a node; and wherein a number of nodes are interconnected providing for each node to sequentially take input data from said network edge until its memories are full and then to change to circuit switched mode providing for another node to take input data.
Claim 12
Dependent Claim
271 words
A network data transfer apparatus, comprising: a network comprising rings of toroidally interconnected nodes, each of said nodes comprising a plurality of interconnected processor-memory elements (PME's) having a processor and a local memory; means for logically breaking said rings along a dimension orthogonal to said rings establishing a network edge; means for dynamic toggling between an edgeless network and an edged network; and means for data transfer into and out of said network through said network edge; wherein breaking of said rings provides a number of network edges equal to the number of orthogonal logical breaks of said rings; wherein said rings connect said nodes in an multi-dimensional orthogonal manner, orthogonal logical breaking of the rings occurs in a plurality of orthogonal dimensions, and data is passed into and out of said network through the multi-dimensional orthogonal ring breaks; wherein said nodes operate in normal and circuit switched modes; normal node providing for data passage through said network edge into or out of memories of a node on said network edge; and circuit switched mode providing for data passage through said network edge and a node on said network edge and into or out of memories of a node not located on said network edge; wherein data is passed through said network edge and through a plurality of nodes before going into or out of memories of a node; and wherein a number of nodes are interconnected providing for each node to sequentially take input data from said network edge until its memories are full and then to change to circuit switched mode providing for another node to take input data.
Claim 13
Dependent Claim
21 words
The apparatus of claim 10, wherein at least one processing element is a processor-memory element (PME) which functions in SIMD/MIMD modes.
Claim 14
Dependent Claim
39 words
The apparatus of claim 10, further comprising: means for dynamically enabling and disabling a circuit switch path through PME's; and means for PME's to determine that a last word of a message has passed through said circuit switch path.
Claim 15
Dependent Claim
19 words
The apparatus of claim 10, further comprising means for alternating data transfer path between a plurality of neighboring nodes.
Claim 16
Dependent Claim
17 words
The apparatus of claim 10, wherein the number of orthogonal logical breaking of the rings is two.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 2000-03-31 | 2000-09-30 | 2001-04-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2004-03-31 | 2004-09-30 | 2005-04-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2008-03-31 | 2008-09-30 | 2009-04-01 | $7700.00 | Window Closed / Lapsed |