Parallel data processing system combining a SIMD unit with a MIMD unit and sharing a common bus, memory, and system controller

Claim 2

A parallel data processing system comprising: a first parallel data processing unit, including a number of interconnected processing elements of a first type and that is directable to execute a single stream of instructions on multiple streams of data, wherein each processing element is capable of storing a quantity of data and of processing an amount of data per unit time; a second parallel data processing unit, including a number of interconnected processing elements of a second type and that is directable to execute multiple streams of instructions on multiple streams of data, wherein each processing element is capable of storing a quantity of data and of processing an amount of data per unit time; a common bus and a common memory connecting said first and second processing units; a system controller having means for directing the first unit to execute the single stream of instructions on multiple streams of data and for directing the second unit to execute the multiple streams of instructions on multiple streams of data; wherein the quantity of data storable in the first type of processing element is less than the quantity of data storable in the second type of processing element; wherein the amount of data processable per unit time by the first type of processing element is less than the amount of data processable per unit time in the second type of processing element; and wherein the number of processing elements of the first type exceeds the number of processing elements of the second type.

Claim 3

A parallel data processing system according to claim 1, wherein said common bus is a high-speed multibus which can be used by each of the parallel data processing units independently, said common memory is a large-capacity high-speed common memory comprising a plurality of segments, each segment being connected to said multibus, said system controller has a data processor for processing user programs, a memory for storing said programs, a disk unit for storing data to be processed, and bus connectors for connecting the controller to said multibus and an internal bus for connecting the data processor, memory, disk unit and bus connector, and said first and second parallel data processing units include input/output controllers for controlling the input and output of data from said multibus.

Claim 4

A parallel data processing system according to claim 1 or claim 2, wherein each of said parallel data processing units is used independently, and operations are performed concurrently by the two processing units on different data within said common memory.

Claim 5

A parallel data processing system according to claim 1 or claim 2 wherein a series of continuous data sets are processed first by the first parallel data processing unit and second by the second parallel processing unit in a sequential pipeline fashion.

Claim 6

A parallel data processing system according to claim 1 or claim 2, wherein said parallel data processing units are operated concurrently and independently on the same data within said common memory.

Claim 7

A parallel data processing system according to claim 1 or claim 2, wherein said system controller allocates neighborhood processings for making calculations between pixels to the first parallel data processing unit, and allocates general operations for making calculations for a whole image to the second parallel data processing unit.

Claim 8

A parallel data processing system comprising: a first parallel data processing unit, including a number of interconnected processing elements of a first type and that is directable to execute a single stream of instructions on multiple streams of data, wherein each processing element has a memory capable of storing a number of bits and an arithmetic unit capable of processing a number of bits per instruction; a second parallel data processing unit, including a number of interconnected processing elements of a second type and that is directable to execute multiple streams of instructions on multiple streams of data, wherein each processing element has a memory capable of storing a number of bits and an arithmetic unit capable of processing a number of bits per instruction; a common bus and a common memory, connecting said first and second processing units; a system controller having means for directing the first unit to execute the single stream of instructions on multiple streams of data and for directing the second unit to execute the multiple streams of instructions on multiple streams of data, and for controlling execution of an application program, the application program containing a function including means for specifying a data processing unit; and said system controller including means, responsive to a specification of a data processing unit, for executing the function including said specification on the specified processing unit; wherein the number of bits per instruction processable by the arithmetic unit in the first type of processing element is less than the number of bits per instruction processable by the arithmetic unit in the second type of processing element.

Claim 9

A parallel data processing system comprising: a first parallel data processing unit, including a number of interconnected processing elements of a first type and that is directable to execute a single stream of instructions on multiple streams of data, wherein each processing element has a memory capable of storing a number of bits and an arithmetic unit capable of processing a number of bits per instruction; a second parallel data processing unit, including a number of interconnected processing elements of a second type and that is directable to execute multiple streams of instructions on multiple streams of data, wherein each processing element has a memory capable of storing a number of bits and an arithmetic unit capable of processing a number of bits per instruction; a common bus and a common memory, connecting said first and second processing units; a system controller having means for directing the first unit to execute the single stream of instructions on multiple streams of data and for directing the second unit to execute the multiple streams of instructions on multiple streams of data, and for controlling execution of an application program, the application program containing a function including means for specifying a data processing unit; and said system controller including means, responsive to a specification of a data processing unit, for executing the function including said specification on the specified processing unit; wherein the number of bits per instruction processable by the arithmetic unit in the first type of processing element is less than the number of bits per instruction processable by the arithmetic unit in the second type of processing element.

Claim 10

A parallel data processing system as set forth in claim 7, further comprising means for temporarily separating the bus from at least one of the first and second parallel data processing units.

Claim 11

A parallel data processing system as set forth in claim 7, further comprising at least a second common bus, and wherein said means for separating the bus includes a connector for each bus for connecting the bus to at least one of the first and second parallel data processing units; and a selector, responsive to a signal from the system controller, for switching and connecting the connectors to one of said common buses and one of the first and second data processing units.

Claim 12

A parallel data processing system as set forth in claim 7, further comprising bus terminating resistors for terminating a separated bus.

Claim 13

A parallel data processing system as set forth in claim 7, wherein said common memory is addressable by a logical segment number and an address, and wherein the system controller performs correspondence between the logical segment numbers and physical segment numbers.

Claim 14

A parallel data processing system as set forth in claim 7, wherein said system controller comprises: a data processor for processing an application program; a memory for storing the application program and data; a bus connector for connecting the system controller to the common bus; and an internal bus for allowing communication between the data processor, memory, and bus connector; said data processor including means for transferring data from the memory to the common memory through the common bus.

Claim 15

A parallel data processing system as set forth in claim 7, wherein the first parallel data processing unit comprises: a plurality of processing elements, wherein adjacent elements are interconnected by a lattice configuration; a system controller for issuing an instruction to said processing elements simultaneously; an input/output controller for transferring data between the common memory and the processing elements in response to instructions from the system controller.

Claim 16

A parallel data processing system as set forth in claim 13, wherein the processing element comprises an arithmetic unit and a local memory for holding data accessible by the arithmetic unit.

Claim 17

A parallel data processing system as set forth in claim 14, wherein the arithmetic unit comprises an adder/subtractor, a register for storing data and a plurality of control flags for controlling operation of the adder/subtractor.

Claim 18

A parallel data processing system as set forth in claim 7, wherein the second data processing unit comprises: a plurality of processing elements; and a system controller for issuing a string of instructions to each of said processing elements; and an input/output controller for transferring data between the common memory and the processing elements in response to instructions from the system controller.

Claim 19

A parallel data processing system as set forth in claim 16, wherein the processing unit comprises: an arithmetic unit; a local memory for storing data accessible by the arithmetic unit; and a controller for executing a string of instructions on the arithmetic unit in response to the system controller.

Claim 20

A parallel data processing system as set forth in claim 7, wherein said first and second data processing units are respectively connected to a common memory via first and second common buses, and respectively use separate segments of the common memory.

Claim 21

A parallel data processing system as set forth in claim 7, wherein the first parallel data processing unit uses data from the common memory to execute a function and wherein the second parallel data processing unit uses said data to perform a different function simultaneously.

Claim 22

A parallel data processing system as set forth in claim 7, wherein the system controller manages resources of the first and second parallel data processing units, manages data within segments of the common memory, manages input and output of data between the common memory and the parallel data processing units so as to enable parallel and pipeline control of the first and second parallel data processing units in a manner transparent to the user.

Claim 23

The parallel data processing system as set forth in claim 7, wherein the means responsive to a specification is a control program.

Claim 24

The parallel data processing system as set forth in claim 21, wherein the means for specifying are codes embedded in the application program by a compiler for delivery to the control program during execution.

Claim 25

The parallel data processing system of claim 7, wherein the number of processing elements of the first type exceeds the number of processing elements of the second type.

Claim 26

The parallel data processing system of claim 23, wherein the quantity of data storable in the first type of processing element is less than the quantity of data storable in the second type of processing element.

Claim 27

The parallel data processing system of claim 7, wherein the number of processing elements in the first unit exceeds the number of processing elements in the second unit by at least two orders of magnitude, wherein the number of bits storable in the memory of the second type of processing element exceeds the number of bits storable in the memory of the first type of processing element by at least two orders of magnitude, wherein the number of bits processable per instruction of the arithmetic unit of the second processing element exceeds the number of bits per instruction of the arithmetic unit of the first processing element by at least a factor of two, and wherein the product of the number of processing elements in the first unit, the number of bits in the memory of the first type of processing element, and the number of bits per instruction of the arithmetic unit of the first processing element equals to within one order of magnitude the product of the number of processing elements in the second unit, the number of bits in the memory of the second type of processing element, and the number of bits per instruction of the arithmetic unit of the second processing element.