Programmable logic module and architecture for field programmable gate array device

Claim 2

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; a second multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to a data input conductor, a control input connected to a second control input conductor, and an output; a third multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to the output of said second multiplexer, a control input connected to a third control input conductor, and an output connected to said data input of said data flip-flop; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said first and second output conductors, said data, clock, and control input conductors of said first, second and third multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said first and second output conductors, said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 3

The programmable logic module of claim 1 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 4

The programmable logic module of claim 1 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 5

The programmable logic module of claim 1 wherein said user-programmable interconnect elements are antifuses.

Claim 6

The programmable logic module of claim 1 further including a first output buffer connected in series between said first output conductor and said general interconnect conductors.

Claim 7

The programmable logic module of claim 5 further including a second output buffer connected in series between said second output conductor and said general interconnect conductors.

Claim 8

The programmable logic module of claim 1 further including at least one logic gate having a plurality of inputs selectively connectable to said general interconnect conductors and an output connected to at least one control input conductor.

Claim 9

A programmable logic module of claim 1 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output connected to a first output conductor.

Claim 10

A programmable logic module of claim 1 wherein said first multiplexer has a first input connected to a first data input conductor, a second input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor and an output connected to a first output conductor.

Claim 11

A programmable logic module of claim 1 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a fifth data input connected to a fifth data input conductor, a sixth data input connected to a sixth data input conductor, a seventh data input connected to a seventh data input conductor, an eighth data input connected to an eighth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor, a third control input connected to a third control input conductor and an output connected to a first output conductor.

Claim 12

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said data flip-flop; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said first and second output conductors, said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said first and second output conductors, said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 13

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said data flip-flop; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said first and second output conductors, said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said first and second output conductors, said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 14

The programmable logic module of claim 11 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 15

The programmable logic module of claim 11 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 16

The programmable logic module of claim 11 wherein said user-programmable interconnect elements are antifuses.

Claim 17

The programmable logic module of claim 11 further including a first output buffer connected in series between said first output conductor and said general interconnect conductors.

Claim 18

The programmable logic module of claim 15 further including a second output buffer connected in series between said second output conductor and said general interconnect conductors.

Claim 19

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data-input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said first and second output conductors, said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said first and second output conductors, said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 20

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data-input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said first and second output conductors, said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said first and second output conductors, said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 21

The programmable logic module of claim 17 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 22

The programmable logic module of claim 17 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 23

The programmable logic module of claim 17 wherein said user-programmable interconnect elements are antifuses.

Claim 24

The programmable logic module of claim 17 further including a first output buffer connected in series between said first output conductor and said general interconnect conductors.

Claim 25

The programmable logic module of claim 21 further including a second output buffer connected in series between said second output conductor and said general interconnect conductors.

Claim 26

The programmable logic module of claim 17 further including at least one logic gate having a plurality of inputs selectively connectable to said general interconnect conductors and an output connected to at least one control input conductor.

Claim 27

The programmable logic module of claim 17 further including a tenth multiplexer having a first data input connected to a ninth data input conductor, a second input connected to a tenth data input conductor, a control input connected to the output of said seventh multiplexer, and an output connected to a third output conductor; and wherein said plurality of general interconnect conductors further intersect at least some of said third output conductors, and said data, clock, and control input conductors of said tenth multiplexer.

Claim 28

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; a second multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to a data input conductor, a control input connected to a second control input conductor, and an output; a third multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to the output of said second multiplexer, a control input connected to a third control input conductor, and an output connected to said data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second and third multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second and third multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 29

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; a second multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to a data input conductor, a control input connected to a second control input conductor, and an output; a third multiplexer having a first data input connected to the output of said data flip-flop, a second data input connected to the output of said second multiplexer, a control input connected to a third control input conductor, and an output connected to said data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second and third multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second and third multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 30

The programmable logic module of claim 25 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 31

The programmable logic module of claim 25 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 32

The programmable logic module of claim 25 wherein said user-programmable interconnect elements are antifuses.

Claim 33

The programmable logic module of claim 25 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 34

The programmable logic module of claim 29 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 35

The programmable logic module of claim 25 further including at least one logic gate having a plurality of inputs selectively connectable to said local and general interconnect conductors and an output connected to at least one control input conductor.

Claim 36

A programmable logic module of claim 25 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output connected to a first output conductor.

Claim 37

A programmable logic module of claim 25 wherein said first multiplexer has a first input connected to a first data input conductor, a second input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor and an output connected to a first output conductor.

Claim 38

A programmable logic module of claim 25 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a fifth data input connected to a fifth data input conductor, a sixth data input connected to a sixth data input conductor, a seventh data input connected to a seventh data input conductor, an eighth data input connected to an eighth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor, a third control input connected to a third control input conductor and an output connected to a first output conductor.

Claim 39

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 40

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; and a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, control input and data control input conductors of said first, second, third, fourth and fifth multiplexers, said first and second control multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 41

The programmable logic module of claim 35 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 42

The programmable logic module of claim 35 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 43

The programmable logic module of claim 35 wherein said user-programmable interconnect elements are antifuses.

Claim 44

The programmable logic module of claim 35 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 45

The programmable logic module of claim 39 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 46

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 47

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth and ninth multiplexers and said data flip-flop, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 48

The programmable logic module of claim 41 wherein said data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 49

The programmable logic module of claim 41 wherein said data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 50

The programmable logic module of claim 41 wherein said user-programmable interconnect elements are antifuses.

Claim 51

The programmable logic module of claim 41 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 52

The programmable logic module of claim 45 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 53

The programmable logic module of claim 41 further including at least one logic gate having a plurality of inputs selectively connectable to said local and general interconnect conductors and an output connected to at least one control input conductor.

Claim 54

The programmable logic module of claim 41 further including a tenth multiplexer having a first data input connected to a ninth data input conductor, a second input connected to a tenth data input conductor, a control input connected to the output of said seventh multiplexer, and an output connected to a third output conductor; wherein said plurality of local interconnect conductors further intersect at least some of said third output conductors, and said data, clock, and control input conductors of said tenth multiplexer; and wherein said plurality of general interconnect conductors further intersect at least some of said third output conductors, and said data, clock, and control input conductors of said tenth multiplexer.

Claim 55

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a first data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; a second multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to a data input conductor, a control input connected to a second control input conductor, and an output; a third multiplexer having a first data input connected to the output of said first data flip-flop, a second data input connected to the output of said second multiplexer, a control input connected to a third control input conductor, and an output connected to said data input of said first data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a fourth multiplexer having a first data input connected to a data input conductor, a second data input connected to a data input conductor, a control input connected to a fourth control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 56

A programmable logic module comprising: a first multiplexer having a plurality of data inputs connected to data input conductors, at least one control input connected to a first control input conductor, and an output connected to a first output conductor; a first data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; a second multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to a data input conductor, a control input connected to a second control input conductor, and an output; a third multiplexer having a first data input connected to the output of said first data flip-flop, a second data input connected to the output of said second multiplexer, a control input connected to a third control input conductor, and an output connected to said data input of said first data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a fourth multiplexer having a first data input connected to a data input conductor, a second data input connected to a data input conductor, a control input connected to a fourth control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said fourth multiplexer, a control input connected to a fifth control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 57

The programmable logic module of claim 49 wherein said first data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 58

The programmable logic module of claim 49 wherein said first data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 59

The programmable logic module of claim 49 wherein said second data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 60

The programmable logic module of claim 49 wherein said second data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 61

The programmable logic module of claim 49 wherein said user-programmable interconnect elements are antifuses.

Claim 62

The programmable logic module of claim 49 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 63

The programmable logic module of claim 55 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 64

The programmable logic module of claim 56 further including a third output buffer connected in series between said third output conductor and said third one of said local interconnect conductors.

Claim 65

The programmable logic module of claim 49 further including at least one logic gate having a plurality of inputs selectively connectable to said local and general interconnect conductors and an output connected to at least one control input conductor.

Claim 66

A programmable logic module of claim 49 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output connected to a first output conductor.

Claim 67

A programmable logic module of claim 49 wherein said first multiplexer has a first input connected to a first data input conductor, a second input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor and an output connected to a first output conductor.

Claim 68

A programmable logic module of claim 49 wherein said first multiplexer has a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a third data input connected to a third data input conductor, a fourth data input connected to a fourth data input conductor, a fifth data input connected to a fifth data input conductor, a sixth data input connected to a sixth data input conductor, a seventh data input connected to a seventh data input conductor, an eighth data input connected to an eighth data input conductor, a first control input connected to a first control input conductor, a second control input connected to a second control input conductor, a third control input connected to a third control input conductor and an output connected to a first output conductor.

Claim 69

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to said output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a first data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said first data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a sixth multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a fifth data input conductor, a control input connected to a fifth control input conductor, and an output; a seventh multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said sixth multiplexer, a control input connected to a sixth control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops and said data control input conductors of said first and second control multiplexers, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops and said data control input conductors of said first and second control multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 70

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input, and an output; a third multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to said output of said second multiplexer, a control input, and an output connected to a first output conductor; a first control multiplexer having an input connected to a first data control input conductor, an inverting input connected to a second data control input conductor, a control input connected to a first control input conductor and an output connected to said control inputs of said first and second multiplexers; a second control multiplexer having an input connected to a third data control input conductor, an inverting input connected to a fourth data control input conductor, a control input connected to a second control input conductor and an output connected to said control input of said third multiplexer; a first data flip-flop having a data input, a clock input, and an output connected to a second output conductor; a fourth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to a fifth data input conductor, a control input connected to a third control input conductor, and an output; a fifth multiplexer having a first data input connected the output of said first data flip-flop, a second data input connected to the output of said fourth multiplexer, a control input connected to a fourth control input conductor, and an output connected to said data input of said first data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a sixth multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a fifth data input conductor, a control input connected to a fifth control input conductor, and an output; a seventh multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said sixth multiplexer, a control input connected to a sixth control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops and said data control input conductors of said first and second control multiplexers, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth and fifth multiplexers and said first and second data flip-flops and said data control input conductors of said first and second control multiplexers, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, control input and data control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 71

The programmable logic module of claim 62 wherein said first data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 72

The programmable logic module of claim 62 wherein said first data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 73

The programmable logic module of claim 62 wherein said second data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 74

The programmable logic module of claim 62 wherein said second data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 75

The programmable logic module of claim 62 wherein said user-programmable interconnect elements are antifuses.

Claim 76

The programmable logic module of claim 62 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 77

The programmable logic module of claim 68 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 78

The programmable logic module of claim 69 further including a third output buffer connected in series between said third output conductor and said third one of said local interconnect conductors.

Claim 79

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a tenth multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a sixth control input conductor, and an output; a eleventh multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said tenth multiplexer, a control input connected to a seventh control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh multiplexers and said first and second data flip-flops, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 80

A programmable logic module comprising: a first multiplexer having a first data input connected to a first data input conductor, a second data input connected to a second data input conductor, a control input connected to a first control input conductor, and an output; a second multiplexer having a first data input connected to a third data input conductor, a second data input connected to a fourth data input conductor, a control input connected to said first control input conductor, and an output; a third multiplexer having a first data input connected to a fifth data input conductor, a second data input connected to a sixth data input conductor, a control input connected to said first control input conductor, and an output; a fourth multiplexer having a first data input connected to a seventh data input conductor, a second data input connected to a eighth data input conductor, a control input connected to said first control input conductor, and an output; a fifth multiplexer having a first data input connected to the output of said first multiplexer, a second data input connected to the output of said second multiplexer, a control input connected to a second control input conductor, and an output; a sixth multiplexer having a first data input connected to the output of said third multiplexer, a second data input connected to the output of said fourth multiplexer, a control input connected to said second control input conductor, and an output; a seventh multiplexer having a first data input connected to the output of said fifth multiplexer, a second data input connected to the output of said sixth multiplexer, a control input connected to a third control input conductor, and an output connected to a first output conductor; a data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a second output conductor; an eighth multiplexer having a first data input connected to the output of said seventh multiplexer, a second data input connected to a ninth data input conductor, a control input connected to a fourth control input conductor, and an output; a ninth multiplexer having a first data input connected the output of said data flip-flop, a second data input connected to said output of said eighth multiplexer, a control input connected to a fifth control input conductor, and an output connected to the data input of said data flip-flop; a second data flip-flop having a data input, a clock input connected to a clock input conductor, and an output connected to a third output conductor; a tenth multiplexer having a first data input connected to a tenth data input conductor, a second data input connected to an eleventh data input conductor, a control input connected to a sixth control input conductor, and an output; a eleventh multiplexer having a first data input connected the output of said second data flip-flop, a second data input connected to said output of said tenth multiplexer, a control input connected to a seventh control input conductor, and an output connected to said data input of said second data flip-flop; a plurality of local interconnect conductors, a first one of said local interconnect conductors connected to said first output conductor, a second local interconnect conductor connected to said second output conductor, a third one of said local interconnect conductors connected to said third output conductor, at least some of said local interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh multiplexers and said first and second data flip-flops, said plurality of local interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; a plurality of general interconnect conductors, at least some of said general interconnect conductors intersecting said data, clock, and control input conductors of said first, second, third, fourth, fifth, sixth, seventh, eighth, ninth, tenth and eleventh multiplexers and said first and second data flip-flops, said plurality of general interconnect conductors selectively connectable to individual ones of said data, clock, and control input conductors by user-programmable interconnect elements; and an inverter having an input connected to a first one of said general interconnect conductors and an output connected to a second one of said general interconnect conductors.

Claim 81

The programmable logic module of claim 71 wherein said first data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 82

The programmable logic module of claim 71 wherein said first data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 83

The programmable logic module of claim 71 wherein said second data flip-flop further includes: a set input connected to a set input conductor, said set input conductor intersecting at least some of said general interconnect conductors and connectable to at least some of said general interconnect conductors by user-programmable interconnect elements.

Claim 84

The programmable logic module of claim 71 wherein said second data flip-flop further includes: a reset input connected to a reset input conductor, said reset input conductor intersecting at least some of said local and general interconnect conductors and connectable to at least some of said local and general interconnect conductors by user-programmable interconnect elements.

Claim 85

The programmable logic module of claim 71 wherein said user-programmable interconnect elements are antifuses.

Claim 86

The programmable logic module of claim 71 further including a first output buffer connected in series between said first output conductor and said first one of said local interconnect conductors.

Claim 87

The programmable logic module of claim 71 further including a second output buffer connected in series between said second output conductor and said second one of said local interconnect conductors.

Claim 88

The programmable logic module of claim 78 further including a third output buffer connected in series between said third output conductor and said third one of said local interconnect conductors.

Claim 89

The programmable logic module of claim 71 further including at least one logic gate having a plurality of inputs selectively connectable to said local and general interconnect conductors and an output connected to at least one control input conductor.

Claim 90

The programmable logic module of claim 71 further including a twelfth multiplexer having a first data input connected to a ninth data input conductor, a second input connected to a tenth data input conductor, a control input connected to the output of said seventh multiplexer, and an output connected to a fourth output conductor; wherein said plurality of local interconnect conductors further intersect at least some of said fourth output conductor, and said data, clock, and control input conductors of said twelfth multiplexer; and wherein said plurality of general interconnect conductors further intersect at least some of said fourth output conductor, and said data, clock, and control input conductors of said twelfth multiplexer.