Phase interleaving control method for a multi-channel regulator system

Claim 2

A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of: (A) during a first state detecting if any external clock appears at an input pin of said pulse width modulation integrated circuit; (B) if a first clock is detected in the step A, then performing the steps of: transiting to a second state for a slave mode; triggering the pulse width modulation signal with the first clock; and generating a second clock synchronous to and phase interleaved with the first clock, and outputting the second clock through an output pin of said pulse width modulation integrated circuit; and (C) if no external clock is detected in the step A, then performing the steps of: transiting to a third state for a master mode; triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit; and generating a third clock synchronous to and phase interleaved with the internal clock, and outputting the third clock through said output pin.

Claim 3

The method of claim 1 , further comprising the step of defining a phase delay based on a phase setting device inside or outside said pulse width modulation integrated circuit.

Claim 4

The method of claim 2 , wherein the second clock is generated using the phase delay.

Claim 5

The method of claim 2 , wherein the third clock is generated using the phase delay.

Claim 6

The method of claim 1 , further comprising the step of defining a phase delay based on a phase setting device on said output pin.

Claim 7

The method of claim 5 , wherein the second clock is generated using the phase delay.

Claim 8

The method of claim 5 , wherein the third clock is generated using the phase delay.

Claim 9

The method of claim 5 , further comprising the step of making said output pin at a preset state during a fourth state.

Claim 10

The method of claim 1 , further comprising the step of defining a phase delay based on a resistor on said output pin.

Claim 11

The method of claim 9 , wherein the second clock is generated using the phase delay.

Claim 12

The method of claim 9 , wherein the third clock is generated using the phase delay.

Claim 13

The method of claim 9 , further comprising the step of making said output pin at a preset state during a fourth state.

Claim 14

The method of claim 1 , further comprising the steps of: if a fourth clock appears at said input pin during the master mode, controlling a phase of the pulse width modulation signal; and when a phase difference between the pulse width modulation signal and the fourth clock becomes less than a threshold, transiting to the second state.

Claim 15

The method of claim 1 , further comprising the step of transiting to the third state if the first clock disappears for a threshold time during the slave mode.

Claim 16

A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of: (A) detecting a phase setting device to define a phase delay during a power on reset of said pulse width modulation integrated circuit; (B) after the power on reset, if a first clock coming from a previous channel is detected, transiting to a first state for a slave mode and triggering the pulse width modulation signal with the first clock, otherwise transiting to a second state for a master mode and triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit; (C) during the slave mode, generating a second clock synchronous to and phase interleaved with the first clock using the phase delay, and once a cycle variation of the first clock reaches a threshold, transiting to the second state and triggering the pulse width modulation signal with the internal clock; and (D) during the master mode, generating a third clock synchronous to and phase interleaved with the internal clock using the phase delay, and once a fourth clock coming from the previous channel is detected, transiting to the first state and triggering the pulse width modulation signal with the fourth clock.

Claim 17

A phase interleaving control method for a multi-channel regulator system including a plurality of pulse width modulation integrated circuits connected in series, each said pulse width modulation integrated circuit determining a pulse width modulation signal for a respective channel, the method comprising operating each said pulse width modulation integrated circuit to perform the steps of: (A) detecting a phase setting device to define a phase delay during a power on reset of said pulse width modulation integrated circuit; (B) after the power on reset, if a first clock coming from a previous channel is detected, transiting to a first state for a slave mode and triggering the pulse width modulation signal with the first clock, otherwise transiting to a second state for a master mode and triggering the pulse width modulation signal with an internal clock of said pulse width modulation integrated circuit; (C) during the slave mode, generating a second clock synchronous to and phase interleaved with the first clock using the phase delay, and once a cycle variation of the first clock reaches a threshold, transiting to the second state and triggering the pulse width modulation signal with the internal clock; and (D) during the master mode, generating a third clock synchronous to and phase interleaved with the internal clock using the phase delay, and once a fourth clock coming from the previous channel is detected, transiting to the first state and triggering the pulse width modulation signal with the fourth clock.

Claim 18

The method of claim 15 , wherein the step D comprises the steps of: upon detecting the fourth clock, controlling a phase of the pulse width modulation signal; and when a phase difference between the pulse width modulation signal and the fourth clock becomes less than a threshold, transiting to the first state.

Claim 19

The method of claim 15 , further comprising the step of transiting to a third state if a sleep signal is detected after the power on reset.

Claim 20

The method of claim 17 , further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.

Claim 21

The method of claim 15 , further comprising the step of transiting to a third state if a sleep signal is detected during the first state.

Claim 22

The method of claim 19 , further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.

Claim 23

The method of claim 15 , further comprising the step of transiting to a third state if a sleep signal is detected during the second state.

Claim 24

The method of claim 21 , further comprising the step of transiting to the second state if the sleep signal disappears for a preset time during the third state.